tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/block_design_wrapper.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library axi;
14 use axi.axi_pkg.all;
15
16 library common;
17 use common.common_pkg.all;
18
19 use work.block_design_pkg.block_design;
20 use work.artyz7_top_pkg.all;
21
22
23
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13248 entity block_design_wrapper is
24 port (
25 clk_m_gp0 : in std_logic;
26 m_gp0_m2s : out axi_m2s_t := axi_m2s_init;
27 m_gp0_s2m : in axi_s2m_t;
28
29 clk_s_hp0 : in std_logic;
30 s_hp0_m2s : in axi_m2s_t;
31
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4446 s_hp0_s2m : out axi_s2m_t := axi_s2m_init;
32 1086
33 pl_clk0 : out std_logic := '0';
34 pl_clk1 : out std_logic := '0'
35
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2226 );
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2166 end entity;
37
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18 architecture a of block_design_wrapper is
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6 begin
40
41 ------------------------------------------------------------------------------
42 block_design_gen : if in_simulation generate
43
44
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18 block_design_mock_inst : entity work.block_design_mock
45 port map (
46 clk_m_gp0 => clk_m_gp0,
47 m_gp0_m2s => m_gp0_m2s,
48 m_gp0_s2m => m_gp0_s2m,
49
50 clk_s_hp0 => clk_s_hp0,
51 s_hp0_m2s => s_hp0_m2s,
52 s_hp0_s2m => s_hp0_s2m,
53
54 pl_clk0 => pl_clk0,
55 pl_clk1 => pl_clk1
56 );
57
58
59 ------------------------------------------------------------------------------
60 else generate
61 6 subtype axi3_len_rng is integer range 3 downto 0;
62
63 subtype m_gp0_id_rng is integer range 11 downto 0;
64 subtype m_gp0_strb_rng is integer range axi_w_strb_width(m_gp0_data_width) - 1 downto 0;
65
66 subtype s_hp0_id_rng is integer range 5 downto 0;
67 subtype s_hp0_data_rng is integer range s_hp0_data_width - 1 downto 0;
68 subtype s_hp0_strb_rng is integer range axi_w_strb_width(s_hp0_data_width) - 1 downto 0;
69 begin
70
71 ----------------------------------------------------------------------------
72 6 block_design_inst : component block_design
73 port map (
74 unsigned(M_AXI_GP0_araddr) => m_gp0_m2s.read.ar.addr(m_gp0_addr_width - 1 downto 0),
75 M_AXI_GP0_arburst => m_gp0_m2s.read.ar.burst,
76 M_AXI_GP0_arcache => open,
77 unsigned(M_AXI_GP0_arid) => m_gp0_m2s.read.ar.id(m_gp0_id_rng),
78 unsigned(M_AXI_GP0_arlen) => m_gp0_m2s.read.ar.len(axi3_len_rng),
79 M_AXI_GP0_arlock => open,
80 M_AXI_GP0_arprot => open,
81 M_AXI_GP0_arqos => open,
82 M_AXI_GP0_arready => m_gp0_s2m.read.ar.ready,
83 unsigned(M_AXI_GP0_arsize) => m_gp0_m2s.read.ar.size,
84 M_AXI_GP0_arvalid => m_gp0_m2s.read.ar.valid,
85 unsigned(M_AXI_GP0_awaddr) => m_gp0_m2s.write.aw.addr(m_gp0_addr_width - 1 downto 0),
86 M_AXI_GP0_awburst => m_gp0_m2s.write.aw.burst,
87 M_AXI_GP0_awcache => open,
88 unsigned(M_AXI_GP0_awid) => m_gp0_m2s.write.aw.id(m_gp0_id_rng),
89 unsigned(M_AXI_GP0_awlen) => m_gp0_m2s.write.aw.len(axi3_len_rng),
90 M_AXI_GP0_awlock => open,
91 M_AXI_GP0_awprot => open,
92 M_AXI_GP0_awqos => open,
93 M_AXI_GP0_awready => m_gp0_s2m.write.aw.ready,
94 unsigned(M_AXI_GP0_awsize) => m_gp0_m2s.write.aw.size,
95 M_AXI_GP0_awvalid => m_gp0_m2s.write.aw.valid,
96 M_AXI_GP0_bid => std_logic_vector(m_gp0_s2m.write.b.id(m_gp0_id_rng)),
97 M_AXI_GP0_bready => m_gp0_m2s.write.b.ready,
98 M_AXI_GP0_bresp => m_gp0_s2m.write.b.resp,
99 M_AXI_GP0_bvalid => m_gp0_s2m.write.b.valid,
100 M_AXI_GP0_rdata => m_gp0_s2m.read.r.data(m_gp0_data_width - 1 downto 0),
101 M_AXI_GP0_rid => std_logic_vector(m_gp0_s2m.read.r.id(m_gp0_id_rng)),
102 M_AXI_GP0_rlast => m_gp0_s2m.read.r.last,
103 M_AXI_GP0_rready => m_gp0_m2s.read.r.ready,
104 M_AXI_GP0_rresp => m_gp0_s2m.read.r.resp,
105 M_AXI_GP0_rvalid => m_gp0_s2m.read.r.valid,
106 M_AXI_GP0_wdata => m_gp0_m2s.write.w.data(m_gp0_data_width - 1 downto 0),
107 M_AXI_GP0_wlast => m_gp0_m2s.write.w.last,
108 M_AXI_GP0_wready => m_gp0_s2m.write.w.ready,
109 M_AXI_GP0_wstrb => m_gp0_m2s.write.w.strb(m_gp0_strb_rng),
110 M_AXI_GP0_wvalid => m_gp0_m2s.write.w.valid,
111 --
112 S_AXI_HP0_arready => s_hp0_s2m.read.ar.ready,
113 S_AXI_HP0_awready => s_hp0_s2m.write.aw.ready,
114 S_AXI_HP0_bvalid => s_hp0_s2m.write.b.valid,
115 S_AXI_HP0_rlast => s_hp0_s2m.read.r.last,
116 S_AXI_HP0_rvalid => s_hp0_s2m.read.r.valid,
117 S_AXI_HP0_wready => s_hp0_s2m.write.w.ready,
118 S_AXI_HP0_bresp => s_hp0_s2m.write.b.resp,
119 S_AXI_HP0_rresp => s_hp0_s2m.read.r.resp,
120 unsigned(S_AXI_HP0_bid) => s_hp0_s2m.write.b.id(s_hp0_id_rng),
121 unsigned(S_AXI_HP0_rid) => s_hp0_s2m.read.r.id(s_hp0_id_rng),
122 S_AXI_HP0_rdata => s_hp0_s2m.read.r.data(s_hp0_data_rng),
123 S_AXI_HP0_arvalid => s_hp0_m2s.read.ar.valid,
124 S_AXI_HP0_awvalid => s_hp0_m2s.write.aw.valid,
125 S_AXI_HP0_bready => s_hp0_m2s.write.b.ready,
126 S_AXI_HP0_rready => s_hp0_m2s.read.r.ready,
127 S_AXI_HP0_wlast => s_hp0_m2s.write.w.last,
128 S_AXI_HP0_wvalid => s_hp0_m2s.write.w.valid,
129 S_AXI_HP0_arburst => s_hp0_m2s.read.ar.burst,
130 S_AXI_HP0_arlock => axi3_a_lock_normal,
131 S_AXI_HP0_arsize => std_logic_vector(s_hp0_m2s.read.ar.size),
132 S_AXI_HP0_awburst => s_hp0_m2s.write.aw.burst,
133 S_AXI_HP0_awlock => axi3_a_lock_normal,
134 S_AXI_HP0_awsize => std_logic_vector(s_hp0_m2s.write.aw.size),
135 S_AXI_HP0_arprot => axi_a_prot_unprivileged or axi_a_prot_secure or axi_a_prot_data,
136 S_AXI_HP0_awprot => axi_a_prot_unprivileged or axi_a_prot_secure or axi_a_prot_data,
137 S_AXI_HP0_araddr => std_logic_vector(s_hp0_m2s.read.ar.addr(s_hp0_addr_width - 1 downto 0)),
138 S_AXI_HP0_awaddr => std_logic_vector(s_hp0_m2s.write.aw.addr(s_hp0_addr_width - 1 downto 0)),
139 S_AXI_HP0_arcache => axi_a_cache_device_non_bufferable,
140 S_AXI_HP0_arlen => std_logic_vector(s_hp0_m2s.read.ar.len(axi3_len_rng)),
141 S_AXI_HP0_arqos => (others => '0'), -- No QoS scheme
142 S_AXI_HP0_awcache => axi_a_cache_device_non_bufferable,
143 S_AXI_HP0_awlen => std_logic_vector(s_hp0_m2s.write.aw.len(axi3_len_rng)),
144 S_AXI_HP0_awqos => (others => '0'), -- No QoS scheme
145 S_AXI_HP0_arid => std_logic_vector(s_hp0_m2s.read.ar.id(s_hp0_id_rng)),
146 S_AXI_HP0_awid => std_logic_vector(s_hp0_m2s.write.aw.id(s_hp0_id_rng)),
147 S_AXI_HP0_wid => (others => '0'), -- Unused function in AXI3
148 S_AXI_HP0_wdata => s_hp0_m2s.write.w.data(s_hp0_data_rng),
149 S_AXI_HP0_wstrb => s_hp0_m2s.write.w.strb(s_hp0_strb_rng),
150 --
151 M_AXI_GP0_ACLK => clk_m_gp0,
152 FCLK_CLK0 => pl_clk0,
153 S_AXI_HP0_ACLK => clk_s_hp0,
154 FCLK_CLK1 => pl_clk1
155 );
156 end generate;
157
158 end architecture;
159