tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/common_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 3 3 100.0%
Branches: 3 6 50.0%

Line Branch Exec Source
1
1/2
✗ Branch 0 not taken.
✓ Branch 1 taken 6 times.
36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12
13 package common_pkg is
14
15 function in_simulation return boolean;
16
17 end package;
18
19 package body common_pkg is
20
21 function in_simulation return boolean is
22 begin
23 -- synthesis translate_off
24 12 return true;
25 -- synthesis translate_on
26
27
2/4
✗ Branch 0 not taken.
✓ Branch 1 taken 6 times.
✗ Branch 3 not taken.
✓ Branch 4 taken 6 times.
12 return false;
28 end function;
29
30 end package body;
31