tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/ddr_buffer/ddr_buffer_regs_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 21 21 100.0%
Branches: 47 78 60.3%

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244 -- This file is automatically generated by tsfpga.
2 -- Generated 2021-07-26 04:02 from file regs_ddr_buffer.toml at commit 90600011cfdfc666.
3 -- Register hash 49f915a733d648eeeeaf2e5de68324355045117c, generator version 1.0.5.
4
5 library ieee;
6 use ieee.std_logic_1164.all;
7 use ieee.numeric_std.all;
8
9 library reg_file;
10 use reg_file.reg_file_pkg.all;
11
12
13 package ddr_buffer_regs_pkg is
14
15 16 constant ddr_buffer_config : natural := 0;
16 16 constant ddr_buffer_command : natural := 1;
17 16 constant ddr_buffer_status : natural := 2;
18 16 constant ddr_buffer_irq_status : natural := 3;
19 16 constant ddr_buffer_irq_mask : natural := 4;
20 16 constant ddr_buffer_version : natural := 5;
21 function ddr_buffer_addrs_read_addr(array_index : natural) return natural;
22 function ddr_buffer_addrs_write_addr(array_index : natural) return natural;
23
24 16 constant ddr_buffer_addrs_array_length : natural := 2;
25
26 -- Declare register map constants here, but define them in body.
27 -- This is done so that functions have been elaborated when they are called.
28 subtype ddr_buffer_reg_range is natural range 0 to 9;
29 constant ddr_buffer_reg_map : reg_definition_vec_t(ddr_buffer_reg_range);
30
31 subtype ddr_buffer_regs_t is reg_vec_t(ddr_buffer_reg_range);
32 constant ddr_buffer_regs_init : ddr_buffer_regs_t;
33
34 subtype ddr_buffer_reg_was_accessed_t is std_logic_vector(ddr_buffer_reg_range);
35
36 16 constant ddr_buffer_command_start : natural := 0;
37
38 16 constant ddr_buffer_status_idle : natural := 0;
39 subtype ddr_buffer_status_counter is natural range 8 downto 1;
40 16 constant ddr_buffer_status_counter_width : positive := 8;
41
42 subtype ddr_buffer_version_version is natural range 7 downto 0;
43 16 constant ddr_buffer_version_version_width : positive := 8;
44
45 16 constant ddr_buffer_constant_axi_data_width : integer := 64;
46 16 constant ddr_buffer_constant_burst_length_beats : integer := 16;
47 16 constant ddr_buffer_constant_version : integer := 3;
48
49 end package;
50
51 package body ddr_buffer_regs_pkg is
52
53 function ddr_buffer_addrs_read_addr(array_index : natural) return natural is
54 begin
55
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106 assert array_index < ddr_buffer_addrs_array_length
56 report "Array index out of bounds: " & natural'image(array_index)
57 severity failure;
58
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106 return 6 + array_index * 2 + 0;
59 end function;
60
61 function ddr_buffer_addrs_write_addr(array_index : natural) return natural is
62 begin
63
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106 assert array_index < ddr_buffer_addrs_array_length
64 report "Array index out of bounds: " & natural'image(array_index)
65 severity failure;
66
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122 return 6 + array_index * 2 + 1;
67 end function;
68
69
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176 constant ddr_buffer_reg_map : reg_definition_vec_t(ddr_buffer_reg_range) := (
70 0 => (idx => ddr_buffer_config, reg_type => r_w),
71 1 => (idx => ddr_buffer_command, reg_type => wpulse),
72 2 => (idx => ddr_buffer_status, reg_type => r),
73 3 => (idx => ddr_buffer_irq_status, reg_type => r_wpulse),
74 4 => (idx => ddr_buffer_irq_mask, reg_type => r_w),
75 5 => (idx => ddr_buffer_version, reg_type => r),
76 6 => (idx => ddr_buffer_addrs_read_addr(0), reg_type => r_w),
77 7 => (idx => ddr_buffer_addrs_write_addr(0), reg_type => r_w),
78 8 => (idx => ddr_buffer_addrs_read_addr(1), reg_type => r_w),
79 9 => (idx => ddr_buffer_addrs_write_addr(1), reg_type => r_w)
80 );
81
82
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176 constant ddr_buffer_regs_init : ddr_buffer_regs_t := (
83 0 => std_logic_vector(to_signed(0, 32)),
84 1 => std_logic_vector(to_signed(0, 32)),
85 2 => std_logic_vector(to_signed(0, 32)),
86 3 => std_logic_vector(to_signed(0, 32)),
87 4 => std_logic_vector(to_signed(0, 32)),
88 5 => std_logic_vector(to_signed(3, 32)),
89 6 => std_logic_vector(to_signed(0, 32)),
90 7 => std_logic_vector(to_signed(0, 32)),
91 8 => std_logic_vector(to_signed(0, 32)),
92 9 => std_logic_vector(to_signed(0, 32))
93 );
94
95 end package body;
96