tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/ddr_buffer/ddr_buffer_sim_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 90 153 58.8%

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128 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12 library vunit_lib;
13 use vunit_lib.random_pkg.all;
14 context vunit_lib.vunit_context;
15 context vunit_lib.vc_context;
16
17 library osvvm;
18 use osvvm.RandomPkg.all;
19
20 library common;
21 use common.addr_pkg.all;
22
23 library reg_file;
24 use reg_file.reg_operations_pkg.all;
25
26 use work.ddr_buffer_regs_pkg.all;
27 use work.example_reg_operations_pkg.all;
28
29
30 package ddr_buffer_sim_pkg is
31
32 procedure run_ddr_buffer_test(signal net : inout network_t;
33 memory : in memory_t;
34 rnd : inout RandomPType;
35 regs_base_address : in addr_t := (others => '0'));
36
37 end package;
38
39 package body ddr_buffer_sim_pkg is
40
41
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240 procedure run_ddr_buffer_test(signal net : inout network_t;
42 memory : in memory_t;
43 rnd : inout RandomPType;
44 regs_base_address : in addr_t := (others => '0')) is
45 6 constant burst_length_bytes : integer :=
46 ddr_buffer_constant_burst_length_beats * (ddr_buffer_constant_axi_data_width / 8);
47 6 variable memory_data : integer_array_t := null_integer_array;
48 6 variable buf : buffer_t;
49 begin
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6 for current_addr_index in 0 to ddr_buffer_addrs_array_length - 1 loop
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24 random_integer_array(rnd, memory_data, width=>burst_length_bytes, bits_per_word=>8);
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53 12 buf := write_integer_array(memory, memory_data, "read data", permissions=>read_only);
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26 write_reg(net, ddr_buffer_addrs_read_addr(current_addr_index), base_address(buf), regs_base_address);
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56 12 buf := set_expected_integer_array(memory, memory_data, "write data", permissions=>write_only);
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48 write_reg(net, ddr_buffer_addrs_write_addr(current_addr_index), base_address(buf), regs_base_address);
58 end loop;
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12 write_command(net, ddr_buffer_command_start, regs_base_address);
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100 wait_for_status_bit(net, ddr_buffer_status_idle, regs_base_address);
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166 check_expected_was_written(memory);
64 end procedure;
65
66 end package body;
67