tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/ddr_buffer/ddr_buffer_top.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 48 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library axi;
14 use axi.axi_pkg.all;
15 use axi.axi_lite_pkg.all;
16
17 library reg_file;
18
19 use work.ddr_buffer_regs_pkg.all;
20
21
22
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13166 entity ddr_buffer_top is
23 port (
24 clk : in std_logic;
25
26 axi_read_m2s : out axi_read_m2s_t := axi_read_m2s_init;
27 axi_read_s2m : in axi_read_s2m_t;
28
29 axi_write_m2s : out axi_write_m2s_t := axi_write_m2s_init;
30 axi_write_s2m : in axi_write_s2m_t;
31 8
32 regs_m2s : in axi_lite_m2s_t;
33
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1608 regs_s2m : out axi_lite_s2m_t := axi_lite_s2m_init
34
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1096 );
35 end entity;
36
37 architecture a of ddr_buffer_top is
38
39 type ctrl_state_t is (idle, start, wait_for_address_transactions, running);
40 8 signal ctrl_state : ctrl_state_t := idle;
41
42 8 signal current_addr_index : integer range 0 to ddr_buffer_addrs_array_length - 1 := 0;
43
44
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7936 signal regs_up, regs_down : ddr_buffer_regs_t := ddr_buffer_regs_init;
45 5288
46 144 signal counter : unsigned(ddr_buffer_status_counter) := (others => '0');
47 168
48
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168 begin
49
50 293 regs_up(ddr_buffer_status)(ddr_buffer_status_counter) <= std_logic_vector(counter);
51
52
53 ------------------------------------------------------------------------------
54
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3927 axi_read_m2s.ar.addr(regs_down(0)'range) <= unsigned(regs_down(ddr_buffer_addrs_read_addr(current_addr_index)));
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144 axi_read_m2s.ar.len <= to_len(ddr_buffer_constant_burst_length_beats);
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64 axi_read_m2s.ar.size <= to_size(ddr_buffer_constant_axi_data_width);
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48 axi_read_m2s.ar.burst <= axi_a_burst_incr;
58
59
60 ------------------------------------------------------------------------------
61
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3927 axi_write_m2s.aw.addr(regs_down(0)'range) <= unsigned(regs_down(ddr_buffer_addrs_write_addr(current_addr_index)));
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144 axi_write_m2s.aw.len <= to_len(ddr_buffer_constant_burst_length_beats);
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64 axi_write_m2s.aw.size <= to_size(ddr_buffer_constant_axi_data_width);
64
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48 axi_write_m2s.aw.burst <= axi_a_burst_incr;
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272 axi_write_m2s.w.strb <= to_strb(ddr_buffer_constant_axi_data_width);
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16 axi_write_m2s.b.ready <= '1';
69
70
71 ------------------------------------------------------------------------------
72
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28 axi_read_m2s.r.ready <= axi_write_s2m.w.ready;
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40 axi_write_m2s.w.valid <= axi_read_s2m.r.valid and axi_read_m2s.r.ready;
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16117 axi_write_m2s.w.data <= axi_read_s2m.r.data;
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1641 axi_write_m2s.w.last <= axi_read_s2m.r.last;
77
78
79 ------------------------------------------------------------------------------
80 8 ctrl : process
81 72 variable ar_done, aw_done : boolean := false;
82 begin
83
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1610 wait until rising_edge(clk);
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85
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401 case ctrl_state is
86 when idle =>
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293 regs_up(ddr_buffer_status)(ddr_buffer_status_idle) <= '1';
88 293 ar_done := false;
89 293 aw_done := false;
90
91
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293 if regs_down(ddr_buffer_command)(ddr_buffer_command_start) then
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3 ctrl_state <= start;
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293 regs_up(ddr_buffer_status)(ddr_buffer_status_idle) <= '0';
94 end if;
95
96 when start =>
97
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6 axi_read_m2s.ar.valid <= '1';
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6 axi_write_m2s.aw.valid <= '1';
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6 ctrl_state <= wait_for_address_transactions;
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101 when wait_for_address_transactions =>
102
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6 if axi_read_m2s.ar.valid and axi_read_s2m.ar.ready then
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6 axi_read_m2s.ar.valid <= '0';
104 6 ar_done := true;
105 end if;
106
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6 if axi_write_m2s.aw.valid and axi_write_s2m.aw.ready then
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6 axi_write_m2s.aw.valid <= '0';
108 6 aw_done := true;
109 end if;
110
111
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6 if ar_done and aw_done then
112
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6 ctrl_state <= running;
113 end if;
114
115 when running =>
116
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96 if axi_write_m2s.w.valid and axi_write_s2m.w.ready and axi_write_m2s.w.last then
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54 counter <= counter + 1;
118
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6 if current_addr_index = ddr_buffer_addrs_array_length - 1 then
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3 current_addr_index <= 0;
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3 ctrl_state <= idle;
122 else
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3 current_addr_index <= current_addr_index + 1;
124
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802 ctrl_state <= start;
125 end if;
126 end if;
127 end case;
128 end process;
129
130
131 ------------------------------------------------------------------------------
132
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16 axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
133 generic map (
134 regs => ddr_buffer_reg_map,
135 default_values => ddr_buffer_regs_init
136 )
137 port map (
138 clk => clk,
139
140 axi_lite_m2s => regs_m2s,
141 axi_lite_s2m => regs_s2m,
142
143 regs_up => regs_up,
144 regs_down => regs_down
145 );
146
147 end architecture;
148