tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/debounce.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 13 13 100.0%
Branches: 23 36 63.9%

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1 18 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Simple debounce mechanism to be used with e.g. the signal from a button or
9 -- dip switch. It eliminates noise by requiring the input to have a stable
10 -- value for a specified number of clock cycles before propagating the value.
11 --
12 -- Uses a resync_level block (async_reg chain) to make sure the input is not
13 -- metastable.
14 -- -------------------------------------------------------------------------------------------------
15
16 library ieee;
17 use ieee.std_logic_1164.all;
18
19 library resync;
20
21
22
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24 entity debounce is
23 generic (
24 -- Number of cycles the input must be stable for the value to propagate to the result side.
25 stable_count : positive
26 );
27 port (
28 -- Input value that may be metastable and noisy
29 noisy_input : in std_logic := '0';
30 --
31 clk : in std_logic;
32 stable_result : out std_logic := '0'
33 );
34 end entity;
35
36 architecture a of debounce is
37
38 3 signal noisy_input_resync : std_logic := '0';
39 6 signal num_cycles_with_new_value : integer range 0 to stable_count - 1 := 0;
40
41 begin
42
43 ------------------------------------------------------------------------------
44
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30246 resync_level_inst : entity resync.resync_level
45 generic map (
46 -- We do not know the input clock, so set this to false
47 enable_input_register => false
48 )
49 port map (
50 data_in => noisy_input,
51 --
52 clk_out => clk,
53 data_out => noisy_input_resync
54 );
55
56
57 ------------------------------------------------------------------------------
58 3 main : process
59 begin
60
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30240 wait until rising_edge(clk);
61
62
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7560 if noisy_input_resync = stable_result then
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4386 num_cycles_with_new_value <= 0;
64
65 else
66
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3174 if num_cycles_with_new_value = stable_count - 1 then
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9 stable_result <= noisy_input_resync;
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9 num_cycles_with_new_value <= 0;
69 else
70
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15123 num_cycles_with_new_value <= num_cycles_with_new_value + 1;
71 end if;
72 end if;
73 end process;
74
75 end architecture;
76