tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/ddr_buffer/example_reg_operations_pkg.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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Branches: 68 127 53.5%

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132 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library vunit_lib;
14 context vunit_lib.vunit_context;
15 context vunit_lib.vc_context;
16
17 library common;
18 use common.addr_pkg.all;
19
20 library reg_file;
21 use reg_file.reg_file_pkg.all;
22 use reg_file.reg_operations_pkg.all;
23
24
25 package example_reg_operations_pkg is
26
27 -- These convenience functions for the example modules rely on using the standard
28 -- register locations, definded below as well as in tsfpga_example_env.py.
29
30 16 constant config_reg : integer := 0;
31 16 constant command_reg : integer := 1;
32 16 constant status_reg : integer := 2;
33 16 constant irq_status_reg : integer := 3;
34 16 constant irq_mask_reg : integer := 4;
35
36 procedure write_command(
37 signal net : inout network_t;
38 bit_index : in natural;
39 base_address : in addr_t := (others => '0')
40 );
41
42 procedure wait_for_status_bit(
43 signal net : inout network_t;
44 bit_index : in natural;
45 base_address : in addr_t := (others => '0')
46 );
47
48 end;
49
50 package body example_reg_operations_pkg is
51
52
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24 procedure write_command(
53 signal net : inout network_t;
54 bit_index : in natural;
55 base_address : in addr_t := (others => '0')
56 ) is
57 begin
58 -- Command is a pulse-type register, so we do not need to do a read-modify-write.
59
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24 write_reg_bit(
60 net=>net,
61 reg_index=>command_reg,
62 bit_index=>bit_index,
63 value=>'1',
64 base_address=>base_address
65 );
66 end procedure;
67
68
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112 procedure wait_for_status_bit(
69 signal net : inout network_t;
70 bit_index : in natural;
71 base_address : in addr_t := (others => '0')
72 ) is
73 begin
74 -- Wait until the indicated status bit is high. The other bits are ignored.
75
76
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128 wait_until_reg_equals_bit(
77 net=>net,
78 reg_index=>status_reg,
79 bit_index=>bit_index,
80 value=>'1',
81 base_address=>base_address
82 );
83 end procedure;
84
85 end;
86