tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/fifo/fifo_netlist_build_wrapper.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 0 16 0.0%
Branches: 0 38 0.0%

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1 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- A wrapper of the FIFO with only the "barebone" ports routed. To be used
9 -- for size assertions in netlist builds.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.numeric_std.all;
14 use ieee.std_logic_1164.all;
15
16
17 entity fifo_netlist_build_wrapper is
18 generic (
19 use_asynchronous_fifo : boolean;
20 width : positive;
21 depth : positive
22 );
23 port (
24 clk : in std_logic;
25 clk_read : in std_logic;
26 clk_write : in std_logic;
27 --
28 read_ready : in std_logic;
29 read_valid : out std_logic := '0';
30 read_data : out std_logic_vector(width - 1 downto 0) := (others => '0');
31 --
32 write_ready : out std_logic := '1';
33 write_valid : in std_logic;
34 write_data : in std_logic_vector(width - 1 downto 0)
35 );
36 end entity;
37
38 architecture a of fifo_netlist_build_wrapper is
39
40 begin
41
42 fifo_wrapper_inst : entity work.fifo_wrapper
43 generic map (
44 use_asynchronous_fifo => use_asynchronous_fifo,
45 width => width,
46 depth => depth
47 )
48 port map (
49 clk => clk,
50 clk_read => clk_read,
51 clk_write => clk_write,
52 --
53 read_ready => read_ready,
54 read_valid => read_valid,
55 read_data => read_data,
56 --
57 write_ready => write_ready,
58 write_valid => write_valid,
59 write_data => write_data
60 );
61
62 end architecture;
63