tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/fifo/fifo_wrapper.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 28 32 87.5%
Branches: 38 85 44.7%

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1 312 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper that selects synchronous/asynchronous FIFO or passthrough depending on on generic values.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14
15 library common;
16 use common.attribute_pkg.all;
17
18
19
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7784 entity fifo_wrapper is
20 generic (
21 use_asynchronous_fifo : boolean;
22 -- Generics for the FIFOs.
23 -- Note that the default values are carefully chosen. Must be exactly the same as in fifo.vhd
24 -- and asynchronous_fifo.vhd.
25 width : positive;
26 depth : natural;
27 almost_full_level : integer range 0 to depth := depth;
28 almost_empty_level : integer range 0 to depth := 0;
29 enable_last : boolean := false;
30 enable_packet_mode : boolean := false;
31 enable_drop_packet : boolean := false;
32 ram_type : ram_style_t := ram_style_auto
33 );
34 port (
35 -- This clock is used for a synchronous FIFO
36 clk : in std_logic;
37 -- These clocks are used for an asynchronous FIFO
38 clk_read : in std_logic := '0';
39 clk_write : in std_logic := '0';
40
41 11 read_ready : in std_logic;
42 read_valid : out std_logic := '0';
43 read_data : out std_logic_vector(width - 1 downto 0) := (others => '0');
44 41 read_last : out std_logic := '0';
45 11
46 -- Note that this is the same as write_level for a synchronous FIFO.
47 52 read_level : out integer range 0 to depth := 0;
48
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4316 -- Note that for an asynchronous FIFO, this signal is in the "read" clock domain.
49 11 almost_empty : out std_logic := '1';
50 1303
51 write_ready : out std_logic := '1';
52 11 write_valid : in std_logic;
53 write_data : in std_logic_vector(width - 1 downto 0);
54 11 write_last : in std_logic := '0';
55
56 -- Note that this is the same as read_level for a synchronous FIFO.
57 11 write_level : out integer range 0 to depth := 0;
58 11 -- Note that for an asynchronous FIFO, this signal is in the "write" clock domain.
59
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428 almost_full : out std_logic := '0';
60
61
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41 -- Note that for an asynchronous FIFO, this signal is in the "write" clock domain
62 drop_packet : in std_logic := '0'
63 11 );
64 end entity;
65
66 115 architecture a of fifo_wrapper is
67 41
68 begin
69
70 41 choose_fifo : if depth = 0 generate
71
72 93 assert not enable_packet_mode report "Can not use packet mode without FIFO";
73 assert not enable_drop_packet report "Can not use drop packet without FIFO";
74 1466
75 write_ready <= read_ready;
76 read_valid <= write_valid;
77 read_data <= write_data;
78
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41 read_last <= write_last;
79
80
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41 elsif use_asynchronous_fifo generate
81
82 41 ------------------------------------------------------------------------------
83
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93 asynchronous_fifo_inst : entity work.asynchronous_fifo
84 generic map (
85 width => width,
86 41 depth => depth,
87 almost_full_level => almost_full_level,
88 almost_empty_level => almost_empty_level,
89 enable_last => enable_last,
90 enable_packet_mode => enable_packet_mode,
91 enable_drop_packet => enable_drop_packet,
92 ram_type => ram_type
93 )
94 port map (
95 clk_read => clk_read,
96 read_ready => read_ready,
97 read_valid => read_valid,
98 read_data => read_data,
99 read_last => read_last,
100 --
101 read_level => read_level,
102 read_almost_empty => almost_empty,
103 --
104 clk_write => clk_write,
105 write_ready => write_ready,
106 write_valid => write_valid,
107 write_data => write_data,
108 write_last => write_last,
109 --
110 write_level => write_level,
111 write_almost_full => almost_full,
112 --
113 drop_packet => drop_packet
114 );
115
116 else generate
117
118 ------------------------------------------------------------------------------
119
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20109 fifo_inst : entity work.fifo
120 generic map (
121 width => width,
122 depth => depth,
123 almost_full_level => almost_full_level,
124 almost_empty_level => almost_empty_level,
125 enable_last => enable_last,
126 enable_packet_mode => enable_packet_mode,
127 enable_drop_packet => enable_drop_packet,
128 ram_type => ram_type
129 )
130 port map (
131 clk => clk,
132 level => read_level,
133 --
134 read_ready => read_ready,
135 read_valid => read_valid,
136 read_data => read_data,
137 read_last => read_last,
138 almost_empty => almost_empty,
139 --
140 write_ready => write_ready,
141 write_valid => write_valid,
142 write_data => write_data,
143 write_last => write_last,
144 almost_full => almost_full,
145 --
146 drop_packet => drop_packet
147 );
148
149
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20087 write_level <= read_level;
150
151 end generate;
152
153
154 end architecture;
155