GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/artyz7/artyz7_regs_pkg.vhd Lines: 21 21 100.0 %
Date: 2021-06-12 04:12:08 Branches: 57 98 58.2 %

Line Branch Exec Source
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-- This file is automatically generated by tsfpga.
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-- Generated 2021-06-12 04:06 from file regs_artyz7.toml at commit 9806b688bef97210.
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-- Register hash 9f09407bc08c4e476fa330876f6f4badf6b78dfd, generator version 1.0.4.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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package artyz7_regs_pkg is
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  constant artyz7_config : natural := 0;
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  constant artyz7_command : natural := 1;
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  constant artyz7_status : natural := 2;
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  constant artyz7_irq_status : natural := 3;
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  constant artyz7_irq_mask : natural := 4;
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  constant artyz7_plain_dummy_reg : natural := 5;
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  function artyz7_dummy_regs_array_dummy_reg(array_index : natural) return natural;
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  function artyz7_dummy_regs_second_array_dummy_reg(array_index : natural) return natural;
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  function artyz7_further_regs_dummy_reg(array_index : natural) return natural;
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  constant artyz7_dummy_regs_array_length : natural := 3;
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  constant artyz7_further_regs_array_length : natural := 1;
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  -- Declare register map constants here, but define them in body.
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  -- This is done so that functions have been elaborated when they are called.
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  subtype artyz7_reg_range is natural range 0 to 12;
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  constant artyz7_reg_map : reg_definition_vec_t(artyz7_reg_range);
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  subtype artyz7_regs_t is reg_vec_t(artyz7_reg_range);
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  constant artyz7_regs_init : artyz7_regs_t;
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  subtype artyz7_reg_was_accessed_t is std_logic_vector(artyz7_reg_range);
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  constant artyz7_plain_dummy_reg_plain_bit_a : natural := 0;
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  constant artyz7_plain_dummy_reg_plain_bit_b : natural := 1;
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  subtype artyz7_plain_dummy_reg_plain_bit_vector is natural range 5 downto 2;
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  constant artyz7_dummy_regs_array_dummy_reg_array_bit_a : natural := 0;
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  constant artyz7_dummy_regs_array_dummy_reg_array_bit_b : natural := 1;
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  subtype artyz7_dummy_regs_array_dummy_reg_array_bit_vector is natural range 5 downto 2;
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end package;
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package body artyz7_regs_pkg is
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  function artyz7_dummy_regs_array_dummy_reg(array_index : natural) return natural is
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  begin
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    assert array_index < artyz7_dummy_regs_array_length
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      report "Array index out of bounds: " & natural'image(array_index)
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      severity failure;
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    return 6 + array_index * 2 + 0;
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  end function;
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  function artyz7_dummy_regs_second_array_dummy_reg(array_index : natural) return natural is
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  begin
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    assert array_index < artyz7_dummy_regs_array_length
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      report "Array index out of bounds: " & natural'image(array_index)
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      severity failure;
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    return 6 + array_index * 2 + 1;
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  end function;
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  function artyz7_further_regs_dummy_reg(array_index : natural) return natural is
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  begin
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    assert array_index < artyz7_further_regs_array_length
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      report "Array index out of bounds: " & natural'image(array_index)
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      severity failure;
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    return 12 + array_index * 1 + 0;
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  end function;
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  constant artyz7_reg_map : reg_definition_vec_t(artyz7_reg_range) := (
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    0 => (idx => artyz7_config, reg_type => r_w),
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    1 => (idx => artyz7_command, reg_type => wpulse),
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    2 => (idx => artyz7_status, reg_type => r),
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    3 => (idx => artyz7_irq_status, reg_type => r_wpulse),
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    4 => (idx => artyz7_irq_mask, reg_type => r_w),
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    5 => (idx => artyz7_plain_dummy_reg, reg_type => r_w),
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    6 => (idx => artyz7_dummy_regs_array_dummy_reg(0), reg_type => r_w),
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    7 => (idx => artyz7_dummy_regs_second_array_dummy_reg(0), reg_type => r),
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    8 => (idx => artyz7_dummy_regs_array_dummy_reg(1), reg_type => r_w),
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    9 => (idx => artyz7_dummy_regs_second_array_dummy_reg(1), reg_type => r),
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    10 => (idx => artyz7_dummy_regs_array_dummy_reg(2), reg_type => r_w),
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    11 => (idx => artyz7_dummy_regs_second_array_dummy_reg(2), reg_type => r),
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    12 => (idx => artyz7_further_regs_dummy_reg(0), reg_type => r_w)
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  );
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  constant artyz7_regs_init : artyz7_regs_t := (
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    0 => std_logic_vector(to_signed(0, 32)),
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    1 => std_logic_vector(to_signed(0, 32)),
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    2 => std_logic_vector(to_signed(0, 32)),
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    3 => std_logic_vector(to_signed(0, 32)),
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    4 => std_logic_vector(to_signed(0, 32)),
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    5 => std_logic_vector(to_signed(14, 32)),
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    6 => std_logic_vector(to_signed(49, 32)),
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    7 => std_logic_vector(to_signed(0, 32)),
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    8 => std_logic_vector(to_signed(49, 32)),
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    9 => std_logic_vector(to_signed(0, 32)),
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    10 => std_logic_vector(to_signed(49, 32)),
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    11 => std_logic_vector(to_signed(0, 32)),
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    12 => std_logic_vector(to_signed(0, 32))
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  );
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end package body;