GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/artyz7/artyz7_top.vhd Lines: 67 67 100.0 %
Date: 2021-06-12 04:12:08 Branches: 345 393 87.8 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library axi;
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use axi.axi_pkg.all;
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use axi.axi_lite_pkg.all;
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library ddr_buffer;
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library fifo;
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library reg_file;
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library resync;
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use work.artyz7_top_pkg.all;
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use work.artyz7_regs_pkg.all;
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7568
entity artyz7_top is
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  port (
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    clk_ext : in std_logic;
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3794
    led : out std_logic_vector(0 to 3) := (others => '0');
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2793
    dummy_output : out std_logic_vector(22 - 1 downto 0) := (others => '0')
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2569
  );
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4004
end entity;
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8321
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architecture a of artyz7_top is
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  signal clk_m_gp0 : std_logic := '0';
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13860
  signal m_gp0_m2s : axi_m2s_t := axi_m2s_init;
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3206
  signal m_gp0_s2m : axi_s2m_t := axi_s2m_init;
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  signal clk_s_hp0 : std_logic := '0';
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2611
  signal s_hp0_m2s : axi_m2s_t := axi_m2s_init;
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1372
  signal s_hp0_s2m : axi_s2m_t := axi_s2m_init;
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  signal regs_m2s : axi_lite_m2s_vec_t(reg_slaves'range) := (others => axi_lite_m2s_init);
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  signal regs_s2m : axi_lite_s2m_vec_t(reg_slaves'range) := (others => axi_lite_s2m_init);
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begin
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  ------------------------------------------------------------------------------
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  blink_0 : process
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    variable count : unsigned(27 - 1 downto 0) := (others => '0');
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  begin
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    wait until rising_edge(clk_m_gp0);
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    led(0) <= count(count'high);
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    count := count + 1;
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  end process;
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  ------------------------------------------------------------------------------
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  blink_1 : process
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    variable count : unsigned(27 - 1 downto 0) := (others => '0');
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  begin
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    wait until rising_edge(clk_s_hp0);
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    led(1) <= count(count'high);
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530
    count := count + 1;
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  end process;
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  ------------------------------------------------------------------------------
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  regs_block : block
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    -- Set up some registers to be in same clock domain as AXI port,
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    -- and some to be in another clock domain.
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    constant clocks_are_the_same : boolean_vector(reg_slaves'range) :=
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      (ddr_buffer_regs_idx => false, dummy_reg_slaves => true);
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  begin
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    ------------------------------------------------------------------------------
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    axi_to_regs_inst : entity axi.axi_to_axi_lite_vec
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      generic map (
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        axi_lite_slaves => reg_slaves,
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        clocks_are_the_same => clocks_are_the_same
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      )
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      port map (
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        clk_axi => clk_m_gp0,
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        axi_m2s => m_gp0_m2s,
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        axi_s2m => m_gp0_s2m,
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        --
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        clk_axi_lite_vec(ddr_buffer_regs_idx) => clk_s_hp0,
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        clk_axi_lite_vec(dummy_reg_slaves) => (dummy_reg_slaves => '0'),
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        axi_lite_m2s_vec => regs_m2s,
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        axi_lite_s2m_vec => regs_s2m
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      );
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    ------------------------------------------------------------------------------
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    register_maps : for slave in dummy_reg_slaves generate
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      axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
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        generic map (
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          regs => artyz7_reg_map,
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          default_values => artyz7_regs_init
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        )
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        port map (
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          clk => clk_m_gp0,
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          --
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          axi_lite_m2s => regs_m2s(slave),
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          axi_lite_s2m => regs_s2m(slave)
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        );
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    end generate;
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  end block;
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  ------------------------------------------------------------------------------
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  ddr_buffer_inst : entity ddr_buffer.ddr_buffer_top
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    port map (
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      clk => clk_s_hp0,
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      --
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      axi_read_m2s => s_hp0_m2s.read,
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      axi_read_s2m => s_hp0_s2m.read,
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      --
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      axi_write_m2s => s_hp0_m2s.write,
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      axi_write_s2m => s_hp0_s2m.write,
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      --
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      regs_m2s => regs_m2s(ddr_buffer_regs_idx),
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      regs_s2m => regs_s2m(ddr_buffer_regs_idx)
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    );
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  ------------------------------------------------------------------------------
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  block_design : block
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7
    signal pl_clk0, pl_clk1 : std_logic := '0';
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  begin
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1088
    clk_m_gp0 <= pl_clk0;
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544
    clk_s_hp0 <= pl_clk1;
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    ------------------------------------------------------------------------------
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    block_design_inst : entity work.block_design_wrapper
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    port map (
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      clk_m_gp0 => clk_m_gp0,
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      m_gp0_m2s => m_gp0_m2s,
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      m_gp0_s2m => m_gp0_s2m,
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      --
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      clk_s_hp0 => clk_s_hp0,
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      s_hp0_m2s => s_hp0_m2s,
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      s_hp0_s2m => s_hp0_s2m,
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      --
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      pl_clk0 => pl_clk0,
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      pl_clk1 => pl_clk1
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    );
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  end block;
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  ------------------------------------------------------------------------------
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  -- Build with an instance of each of the available resync block. To show that the constraints work
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  -- and the build passes timing.
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  resync_test_block : block
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623
    signal misc_dummy_input, dummy_output_m1 : std_logic_vector(dummy_output'range) :=
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      (others => '0');
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    -- Dummy signal in clk_ext domain
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7
    signal sample_value : std_logic := '0';
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  begin
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    -- Some dummy logic that instantiates a lot of the resync blocks.
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    -- All resync should be from internal clock to clk_ext.
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    assign_output : process
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    begin
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      wait until rising_edge(clk_ext);
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      dummy_output <= dummy_output_m1;
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    end process;
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    -- Dummy bits for input.
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    -- Do not use more than the 32 bits that are actually assigned by the register bus.
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    -- Vivado will strip the logic since input will be '-'.
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1179
    misc_dummy_input <= regs_m2s(ddr_buffer_regs_idx).write.w.data(misc_dummy_input'range);
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    ------------------------------------------------------------------------------
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    resync_counter_inst : entity resync.resync_counter
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      generic map (
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        width => 4
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      )
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      port map (
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        clk_in => clk_s_hp0,
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        counter_in => unsigned(misc_dummy_input(3 downto 0)),
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        --
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        clk_out => clk_ext,
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        std_logic_vector(counter_out) => dummy_output_m1(3 downto 0)
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      );
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    ------------------------------------------------------------------------------
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    resync_cycles_inst : entity resync.resync_cycles
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      generic map (
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        counter_width => 8
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      )
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      port map (
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        clk_in => clk_s_hp0,
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        data_in => misc_dummy_input(4),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(4)
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      );
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    ------------------------------------------------------------------------------
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    resync_level_on_signal_inst : entity resync.resync_level_on_signal
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      port map (
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        data_in => misc_dummy_input(5),
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        --
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        clk_out => clk_ext,
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        sample_value => sample_value,
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        data_out => dummy_output_m1(5)
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      );
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    ------------------------------------------------------------------------------
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    resync_level_with_clk_in_inst : entity resync.resync_level
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      generic map (
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        enable_input_register => false
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      )
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      port map (
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        clk_in => clk_s_hp0,
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        data_in => misc_dummy_input(6),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(6)
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      );
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    ------------------------------------------------------------------------------
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    resync_level_with_clk_in_and_input_register_inst : entity resync.resync_level
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      generic map (
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        enable_input_register => true
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      )
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      port map (
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        clk_in => clk_s_hp0,
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        data_in => misc_dummy_input(7),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(7)
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      );
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    ------------------------------------------------------------------------------
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    resync_level_without_clk_in_inst : entity resync.resync_level
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      generic map (
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        enable_input_register => false
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      )
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      port map (
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        data_in => misc_dummy_input(8),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(8)
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      );
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    sample_value <= dummy_output(8);
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    ------------------------------------------------------------------------------
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    resync_slv_level_on_signal_inst : entity resync.resync_slv_level_on_signal
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      generic map (
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        width => 2
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      )
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      port map (
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        data_in => misc_dummy_input(10 downto 9),
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        --
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        clk_out => clk_ext,
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        sample_value => sample_value,
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        data_out => dummy_output_m1(10 downto 9)
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      );
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    ------------------------------------------------------------------------------
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    resync_slv_level_without_clk_in_inst : entity resync.resync_slv_level
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      generic map (
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        width => 2,
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        enable_input_register => false
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      )
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      port map (
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        data_in => misc_dummy_input(12 downto 11),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(12 downto 11)
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      );
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    ------------------------------------------------------------------------------
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    resync_slv_level_with_input_register_inst : entity resync.resync_slv_level
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      generic map (
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        width => 2,
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        enable_input_register => true
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      )
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      port map (
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        clk_in => clk_s_hp0,
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        data_in => misc_dummy_input(14 downto 13),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(14 downto 13)
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      );
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    ------------------------------------------------------------------------------
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    resync_slv_level_coherent_inst : entity resync.resync_slv_level_coherent
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      generic map (
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        width => 2
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      )
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      port map (
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        clk_in => clk_s_hp0,
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        data_in => misc_dummy_input(16 downto 15),
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        --
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        clk_out => clk_ext,
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        data_out => dummy_output_m1(16 downto 15)
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      );
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    ------------------------------------------------------------------------------
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    asynchronous_fifo_block : block
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      -- We need to use a somewhat wide word in order to get Vivado to pack data in BRAM.
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      -- We do no want to use the same bits as some other resync, so for FIFO we use another
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      -- dummy input word.
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      alias fifo_dummy_input is regs_m2s(dummy_reg_slaves'low).write.w.data;
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      signal deep_read_data, shallow_read_data : std_logic_vector(16 - 1 downto 0) :=
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        (others => '0');
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      signal fifo_write_valid, fifo_read_ready : std_logic := '0';
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    begin
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      fifo_write_valid <=
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        regs_s2m(dummy_reg_slaves'low).write.w.ready
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        and regs_m2s(dummy_reg_slaves'low).write.w.valid;
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      dummy_output_m1(17) <= xor deep_read_data;
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      dummy_output_m1(18) <= xor shallow_read_data;
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      ------------------------------------------------------------------------------
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      deep_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
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        generic map (
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          width => deep_read_data'length,
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          -- Depth is selected to create a BRAM
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          depth => 1024
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        )
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        port map (
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          clk_read => clk_ext,
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          read_ready => fifo_read_ready,
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          read_valid => open,
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          read_data => deep_read_data,
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          --
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          clk_write => clk_m_gp0,
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          write_ready => open,
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          write_valid => fifo_write_valid,
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          write_data => fifo_dummy_input(31 downto 16)
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        );
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      ------------------------------------------------------------------------------
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      shallow_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
361
        generic map (
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          width => shallow_read_data'length,
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          -- Depth is selected to create a LUTRAM
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          depth => 16
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        )
366
        port map (
367
          clk_read => clk_ext,
368
          read_ready => fifo_read_ready,
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          read_valid => open,
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          read_data => shallow_read_data,
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          --
372
          clk_write => clk_m_gp0,
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          write_ready => open,
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          write_valid => fifo_write_valid,
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          write_data => fifo_dummy_input(15 downto 0)
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        );
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      ------------------------------------------------------------------------------
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      resync_pulse_inst : entity resync.resync_pulse
381
        port map (
382
          clk_in => clk_m_gp0,
383
          pulse_in => fifo_write_valid,
384
          --
385
          clk_out => clk_ext,
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          pulse_out => fifo_read_ready
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        );
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    end block;
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  end block;
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end architecture;