GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/artyz7/block_design_mock.vhd Lines: 20 20 100.0 %
Date: 2021-06-12 04:12:08 Branches: 206 237 86.9 %

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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library axi;
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use axi.axi_pkg.all;
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library bfm;
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library reg_file;
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use reg_file.reg_operations_pkg.all;
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use work.top_level_sim_pkg.all;
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use work.artyz7_top_pkg.all;
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entity block_design_mock is
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  port (
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    clk_m_gp0 : in std_logic;
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    m_gp0_m2s : out axi_m2s_t;
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    m_gp0_s2m : in axi_s2m_t;
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    clk_s_hp0 : in std_logic;
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    s_hp0_m2s : in axi_m2s_t;
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    s_hp0_s2m : out axi_s2m_t;
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    pl_clk0 : out std_logic := '0';
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    pl_clk1 : out std_logic := '0'
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  );
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end entity;
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architecture a of block_design_mock is
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  constant pl_clk0_period : time := 10 ns; -- 100 MHz
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  constant pl_clk1_period : time := 5 ns; -- 200 MHz
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  constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
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    address_fifo_depth => 1,
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    memory => axi_memory
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  );
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begin
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  pl_clk0 <= not pl_clk0 after pl_clk0_period / 2;
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  pl_clk1 <= not pl_clk1 after pl_clk1_period / 2;
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  ------------------------------------------------------------------------------
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  -- If our register AXI master port used different dimensions than these
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  -- we would need to create another bus master, probably in top_level_sim_pkg.
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  assert m_gp0_data_width = data_length(regs_bus_master);
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  assert m_gp0_addr_width = address_length(regs_bus_master);
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  axi_master_inst : entity bfm.axi_master
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  generic map (
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    bus_handle => regs_bus_master
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  )
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  port map (
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    clk => clk_m_gp0,
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    axi_read_m2s => m_gp0_m2s.read,
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    axi_read_s2m =>  m_gp0_s2m.read,
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    axi_write_m2s => m_gp0_m2s.write,
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    axi_write_s2m =>  m_gp0_s2m.write
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  );
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  ------------------------------------------------------------------------------
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  axi_slave_inst : entity bfm.axi_slave
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    generic map (
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      axi_read_slave => axi_read_slave,
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      axi_write_slave => axi_write_slave,
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      data_width => 64
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    )
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    port map (
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      clk => clk_s_hp0,
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      axi_read_m2s => s_hp0_m2s.read,
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      axi_read_s2m => s_hp0_s2m.read,
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      axi_write_m2s => s_hp0_m2s.write,
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      axi_write_s2m => s_hp0_s2m.write
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    );
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end architecture;