GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/artyz7/tb_artyz7_top.vhd Lines: 76 76 100.0 %
Date: 2021-06-12 04:12:08 Branches: 238 354 67.2 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library vunit_lib;
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use vunit_lib.memory_utils_pkg.all;
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use vunit_lib.random_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library common;
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use common.addr_pkg.all;
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library ddr_buffer;
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use ddr_buffer.ddr_buffer_regs_pkg.all;
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use ddr_buffer.ddr_buffer_sim_pkg.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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use reg_file.reg_operations_pkg.all;
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use work.artyz7_top_pkg.all;
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use work.artyz7_regs_pkg.all;
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use work.top_level_sim_pkg.all;
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entity tb_artyz7_top is
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  generic (
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_artyz7_top is
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  signal clk_ext : std_logic := '0';
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begin
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  test_runner_watchdog(runner, 200 us);
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  clk_ext <= not clk_ext after 8 ns;
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  ------------------------------------------------------------------------------
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  main : process
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    constant beef : reg_t := x"beef_beef";
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    constant dead : reg_t := x"dead_dead";
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    variable reg_value : reg_t := (others => '0');
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    constant axi_width : integer := 64;
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    constant burst_length : integer := 16;
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    constant burst_size_bytes : integer := burst_length * axi_width / 8;
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    variable rnd : RandomPType;
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    variable memory_data : integer_array_t := null_integer_array;
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    variable buf : buffer_t;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    if run("test_register_read_write") then
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      write_reg(net, 0, beef, base_address => reg_slaves(0).addr);
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      check_reg_equal(net, 0, beef, base_address => reg_slaves(0).addr);
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      -- Write different value to same register in another register map.
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      -- Should be in another clock domain to verify CDC.
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      write_reg(net, 0, dead, base_address => reg_slaves(ddr_buffer_regs_idx).addr);
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      check_reg_equal(net, 0, dead, base_address => reg_slaves(ddr_buffer_regs_idx).addr);
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      check_reg_equal(net, 0, beef, base_address => reg_slaves(0).addr);
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    elsif run("test_ddr_buffer") then
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      run_ddr_buffer_test(net, axi_memory, rnd, ddr_buffer_regs_base_addr);
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      check_expected_was_written(axi_memory);
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    elsif run("test_generated_register_adresses") then
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      -- Default register
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      check_equal(artyz7_config, 0, line_num => 89, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_command, 1, line_num => 90, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_status, 2, line_num => 91, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_irq_status, 3, line_num => 92, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_irq_mask, 4, line_num => 93, file_name => "tb_artyz7_top.vhd");
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      -- Plain register from TOML
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      check_equal(artyz7_plain_dummy_reg, 5, line_num => 96, file_name => "tb_artyz7_top.vhd");
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      -- Register array from TOML
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      check_equal(artyz7_dummy_regs_array_length, 3, line_num => 99, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_array_dummy_reg(0), 6, line_num => 101, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_second_array_dummy_reg(0), 7, line_num => 102, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_array_dummy_reg(1), 8, line_num => 103, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_second_array_dummy_reg(1), 9, line_num => 104, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_array_dummy_reg(2), 10, line_num => 105, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_second_array_dummy_reg(2), 11, line_num => 106, file_name => "tb_artyz7_top.vhd");
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    elsif run("test_generated_register_modes") then
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      -- Default register
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      assert artyz7_reg_map(artyz7_config).reg_type = r_w;
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      assert artyz7_reg_map(artyz7_command).reg_type = wpulse;
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      assert artyz7_reg_map(artyz7_status).reg_type = r;
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      assert artyz7_reg_map(artyz7_irq_status).reg_type = r_wpulse;
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      assert artyz7_reg_map(artyz7_irq_mask).reg_type = r_w;
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      -- Plain register from TOML
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      assert artyz7_reg_map(artyz7_plain_dummy_reg).reg_type = r_w;
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      -- Register array from TOML
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      assert artyz7_reg_map(artyz7_dummy_regs_array_dummy_reg(0)).reg_type = r_w;
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      assert artyz7_reg_map(artyz7_dummy_regs_second_array_dummy_reg(0)).reg_type = r;
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      assert artyz7_reg_map(artyz7_dummy_regs_array_dummy_reg(1)).reg_type = r_w;
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      assert artyz7_reg_map(artyz7_dummy_regs_second_array_dummy_reg(1)).reg_type = r;
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      assert artyz7_reg_map(artyz7_dummy_regs_array_dummy_reg(2)).reg_type = r_w;
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      assert artyz7_reg_map(artyz7_dummy_regs_second_array_dummy_reg(2)).reg_type = r;
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    elsif run("test_generated_register_field_indexes") then
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      -- Generated bit field indexes should match the order and widths in the TOML
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      -- Fields in the plain register
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      check_equal(artyz7_plain_dummy_reg_plain_bit_a, 0, line_num => 131, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_plain_dummy_reg_plain_bit_b, 1, line_num => 132, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_plain_dummy_reg_plain_bit_vector'low, 2, line_num => 133, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_plain_dummy_reg_plain_bit_vector'high, 5, line_num => 134, file_name => "tb_artyz7_top.vhd");
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      -- Fields in the register array register
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      check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_a, 0, line_num => 137, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_b, 1, line_num => 138, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_vector'low, 2, line_num => 139, file_name => "tb_artyz7_top.vhd");
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      check_equal(artyz7_dummy_regs_array_dummy_reg_array_bit_vector'high, 5, line_num => 140, file_name => "tb_artyz7_top.vhd");
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    elsif run("test_generated_register_default_values") then
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      -- Test reading the default values set in the regs TOML
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      read_reg(
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        net,
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        artyz7_plain_dummy_reg,
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        reg_value,
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        base_address => reg_slaves(0).addr
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      );
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      check_equal(reg_value(artyz7_plain_dummy_reg_plain_bit_a), '0', line_num => 152, file_name => "tb_artyz7_top.vhd");
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      check_equal(reg_value(artyz7_plain_dummy_reg_plain_bit_b), '1', line_num => 153, file_name => "tb_artyz7_top.vhd");
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      check_equal(unsigned(reg_value(artyz7_plain_dummy_reg_plain_bit_vector)), 3, line_num => 154, file_name => "tb_artyz7_top.vhd");
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      for register_array_idx in 0 to 3 - 1 loop
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        read_reg(
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          net,
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          artyz7_dummy_regs_array_dummy_reg(register_array_idx),
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          reg_value,
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          base_address => reg_slaves(0).addr
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        );
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        check_equal(reg_value(artyz7_plain_dummy_reg_plain_bit_a), '1', line_num => 164, file_name => "tb_artyz7_top.vhd");
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        check_equal(reg_value(artyz7_plain_dummy_reg_plain_bit_b), '0', line_num => 165, file_name => "tb_artyz7_top.vhd");
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        check_equal(unsigned(reg_value(artyz7_plain_dummy_reg_plain_bit_vector)), 12, line_num => 166, file_name => "tb_artyz7_top.vhd");
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      end loop;
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.artyz7_top
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  port map (
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    clk_ext => clk_ext
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  );
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end architecture;