GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_lite_cdc.vhd Lines: 34 34 100.0 %
Date: 2021-06-12 04:12:08 Branches: 192 277 69.3 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Clock crossing of an AXI-Lite bus
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library common;
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use common.attribute_pkg.all;
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library fifo;
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use work.axi_lite_pkg.all;
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use work.axi_pkg.all;
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31892
entity axi_lite_cdc is
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  generic (
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    data_width : positive;
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    addr_width : positive;
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    fifo_depth : positive := 16;
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    ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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    clk_master : in std_logic;
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    master_m2s : in axi_lite_m2s_t;
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    master_s2m : out axi_lite_s2m_t := axi_lite_s2m_init;
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    --
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    clk_slave : in std_logic;
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    slave_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
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    slave_s2m : in axi_lite_s2m_t
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  );
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end entity;
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architecture a of axi_lite_cdc is
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90
begin
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90
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  ------------------------------------------------------------------------------
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  aw_block : block
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6428
    signal read_data, write_data : std_logic_vector(addr_width - 1 downto 0);
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  begin
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90
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316979
    slave_m2s.write.aw.addr(read_data'range) <= unsigned(read_data);
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159567
    write_data <= std_logic_vector(master_m2s.write.aw.addr(write_data'range));
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    aw_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
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      generic map (
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        width => axi_lite_m2s_a_sz(addr_width),
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        depth => fifo_depth,
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        ram_type => ram_type
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      )
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      port map(
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        clk_read => clk_slave,
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        read_ready => slave_s2m.write.aw.ready,
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        read_valid => slave_m2s.write.aw.valid,
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        read_data => read_data,
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        --
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        clk_write => clk_master,
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        write_ready => master_s2m.write.aw.ready,
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        write_valid => master_m2s.write.aw.valid,
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        write_data => write_data
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  w_block : block
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    constant w_width : integer := axi_lite_m2s_w_sz(data_width);
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1314
    signal write_data, read_data : std_logic_vector(w_width - 1 downto 0);
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  begin
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811678
    slave_m2s.write.w.data <= to_axi_lite_m2s_w(read_data, data_width).data;
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112932
    slave_m2s.write.w.strb <= to_axi_lite_m2s_w(read_data, data_width).strb;
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693878
    write_data <= to_slv(master_m2s.write.w, data_width);
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    w_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
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      generic map (
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75158
        width => w_width,
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        depth => fifo_depth,
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        ram_type => ram_type
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      )
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      port map(
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        clk_read => clk_slave,
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        read_ready => slave_s2m.write.w.ready,
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        read_valid => slave_m2s.write.w.valid,
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        read_data => read_data,
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        --
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        clk_write => clk_master,
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        write_ready => master_s2m.write.w.ready,
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        write_valid => master_m2s.write.w.valid,
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        write_data => write_data
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  b_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
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    generic map (
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      width => axi_lite_s2m_b_sz,
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      depth => fifo_depth,
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      ram_type => ram_type
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    )
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    port map(
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      clk_read => clk_master,
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      read_ready => master_m2s.write.b.ready,
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      read_valid => master_s2m.write.b.valid,
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      read_data => master_s2m.write.b.resp,
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      --
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      clk_write => clk_slave,
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      write_ready => slave_m2s.write.b.ready,
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      write_valid => slave_s2m.write.b.valid,
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      write_data => slave_s2m.write.b.resp
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    );
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  ------------------------------------------------------------------------------
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  ar_block : block
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    signal read_data, write_data : std_logic_vector(addr_width - 1 downto 0);
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  begin
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629468
    slave_m2s.read.ar.addr(read_data'range) <= unsigned(read_data);
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163680
    write_data <= std_logic_vector(master_m2s.read.ar.addr(write_data'range));
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    ar_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
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      generic map (
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        width => axi_lite_m2s_a_sz(addr_width),
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        depth => fifo_depth,
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        ram_type => ram_type
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      )
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      port map(
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        clk_read => clk_slave,
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        read_ready => slave_s2m.read.ar.ready,
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        read_valid => slave_m2s.read.ar.valid,
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        read_data => read_data,
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        --
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        clk_write => clk_master,
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        write_ready => master_s2m.read.ar.ready,
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        write_valid => master_m2s.read.ar.valid,
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        write_data => write_data
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  r_block : block
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    constant r_width : integer := axi_lite_s2m_r_sz(data_width);
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    signal read_data, write_data : std_logic_vector(r_width - 1 downto 0);
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  begin
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1643474
    master_s2m.read.r.data <= to_axi_lite_s2m_r(read_data, data_width).data;
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38262
    master_s2m.read.r.resp <= to_axi_lite_s2m_r(read_data, data_width).resp;
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440508
    write_data <= to_slv(slave_s2m.read.r, data_width);
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    r_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
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      generic map (
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        width => r_width,
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        depth => fifo_depth,
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        ram_type => ram_type
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      )
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      port map(
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        clk_read => clk_master,
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        read_ready => master_m2s.read.r.ready,
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        read_valid => master_s2m.read.r.valid,
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        read_data => read_data,
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        --
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        clk_write => clk_slave,
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        write_ready => slave_m2s.read.r.ready,
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        write_valid => slave_s2m.read.r.valid,
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        write_data => write_data
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      );
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  end block;
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end architecture;