GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_lite_pipeline.vhd Lines: 32 32 100.0 %
Date: 2021-06-12 04:12:08 Branches: 117 162 72.2 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Pipelining of an AXI-Lite bus. Uses skid buffers so that full throughput is
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-- sustained.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library common;
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use work.axi_lite_pkg.all;
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use work.axi_pkg.all;
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4248
entity axi_lite_pipeline is
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  generic (
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    data_width : positive;
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    addr_width : positive
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  );
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  port (
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    clk : in std_logic;
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    --
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    master_m2s : in axi_lite_m2s_t;
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    master_s2m : out axi_lite_s2m_t := axi_lite_s2m_init;
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    --
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    slave_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
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    slave_s2m : in axi_lite_s2m_t
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  );
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end entity;
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architecture a of axi_lite_pipeline is
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13180
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begin
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  ------------------------------------------------------------------------------
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  aw_block : block
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    signal output_data, input_data : std_logic_vector(addr_width - 1 downto 0);
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  begin
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54008
    slave_m2s.write.aw.addr(output_data'range) <= unsigned(output_data);
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51920
    input_data <= std_logic_vector(master_m2s.write.aw.addr(input_data'range));
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    aw_handshake_pipeline_inst : entity common.handshake_pipeline
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      generic map (
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        data_width => axi_lite_m2s_a_sz(addr_width)
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      )
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      port map(
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        clk => clk,
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        --
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        input_ready => master_s2m.write.aw.ready,
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        input_valid => master_m2s.write.aw.valid,
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        input_data => input_data,
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        --
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        output_ready => slave_s2m.write.aw.ready,
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        output_valid => slave_m2s.write.aw.valid,
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        output_data => output_data
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  w_block : block
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    constant w_width : integer := axi_lite_m2s_w_sz(data_width);
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    signal master_m2s_w, slave_m2s_w : std_logic_vector(w_width - 1 downto 0);
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  begin
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270324
    slave_m2s.write.w.data <= to_axi_lite_m2s_w(slave_m2s_w, data_width).data;
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18648
    slave_m2s.write.w.strb <= to_axi_lite_m2s_w(slave_m2s_w, data_width).strb;
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231283
    master_m2s_w <= to_slv(master_m2s.write.w, data_width);
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    handshake_pipeline_inst : entity common.handshake_pipeline
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      generic map (
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        data_width => w_width
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      )
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      port map(
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        clk => clk,
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        --
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        input_ready => master_s2m.write.w.ready,
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        input_valid => master_m2s.write.w.valid,
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        input_data => master_m2s_w,
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        --
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        output_ready => slave_s2m.write.w.ready,
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        output_valid => slave_m2s.write.w.valid,
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        output_data => slave_m2s_w
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  b_handshake_pipeline_inst : entity common.handshake_pipeline
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    generic map (
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      data_width => axi_lite_s2m_b_sz
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    )
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    port map(
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      clk => clk,
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      --
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      input_ready => slave_m2s.write.b.ready,
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      input_valid => slave_s2m.write.b.valid,
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      input_data => slave_s2m.write.b.resp,
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      --
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      output_ready => master_m2s.write.b.ready,
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      output_valid => master_s2m.write.b.valid,
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      output_data => master_s2m.write.b.resp
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    );
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  ------------------------------------------------------------------------------
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  ar_block : block
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    signal output_data, input_data : std_logic_vector(addr_width - 1 downto 0);
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  begin
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106904
    slave_m2s.read.ar.addr(output_data'range) <= unsigned(output_data);
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52432
    input_data <= std_logic_vector(master_m2s.read.ar.addr(input_data'range));
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    ar_handshake_pipeline_inst : entity common.handshake_pipeline
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      generic map (
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        data_width => axi_lite_m2s_a_sz(addr_width)
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      )
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      port map(
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        clk => clk,
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        --
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        input_ready => master_s2m.read.ar.ready,
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        input_valid => master_m2s.read.ar.valid,
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        input_data => input_data,
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        --
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        output_ready => slave_s2m.read.ar.ready,
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        output_valid => slave_m2s.read.ar.valid,
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        output_data => output_data
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  r_block : block
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    constant r_width : integer := axi_lite_s2m_r_sz(data_width);
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    signal master_s2m_r, slave_s2m_r : std_logic_vector(r_width - 1 downto 0);
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  begin
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270320
    master_s2m.read.r.data <= to_axi_lite_s2m_r(master_s2m_r, data_width).data;
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6260
    master_s2m.read.r.resp <= to_axi_lite_s2m_r(master_s2m_r, data_width).resp;
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152942
    slave_s2m_r <= to_slv(slave_s2m.read.r, data_width);
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    handshake_pipeline_inst : entity common.handshake_pipeline
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      generic map (
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        data_width => r_width
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      )
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      port map(
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        clk => clk,
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        --
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        input_ready => slave_m2s.read.r.ready,
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        input_valid => slave_s2m.read.r.valid,
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        input_data => slave_s2m_r,
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        --
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        output_ready => master_m2s.read.r.ready,
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        output_valid => master_s2m.read.r.valid,
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        output_data => master_s2m_r
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      );
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  end block;
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end architecture;