GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_lite_pkg.vhd Lines: 65 65 100.0 %
Date: 2021-06-12 04:12:08 Branches: 112 203 55.2 %

Line Branch Exec Source
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380588
-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Data types for working with AXI4-Lite interfaces.
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-- Based on the document "ARM IHI 0022E (ID022613): AMBA AXI and ACE Protocol Specification"
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-- Available here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi_pkg.all;
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package axi_lite_pkg is
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  ------------------------------------------------------------------------------
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  -- A (Address Read and Address Write) channels
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  ------------------------------------------------------------------------------
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  type axi_lite_m2s_a_t is record
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    valid : std_logic;
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    addr : unsigned(axi_a_addr_sz - 1 downto 0);
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    -- Excluded members: prot
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    -- These are typically not changed on a transfer-to-transfer basis.
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  end record;
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5330
  constant axi_lite_m2s_a_init : axi_lite_m2s_a_t := (valid => '0', others => (others => '0'));
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  function axi_lite_m2s_a_sz(addr_width : positive) return positive;
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  type axi_lite_s2m_a_t is record
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    ready : std_logic;
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  end record;
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  constant axi_lite_s2m_a_init : axi_lite_s2m_a_t := (ready => '0');
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  ------------------------------------------------------------------------------
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  -- W (Write Data) channels
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  ------------------------------------------------------------------------------
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  -- Max values
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  constant axi_lite_data_sz : positive := 64;
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  constant axi_lite_w_strb_sz : positive := axi_lite_data_sz / 8;
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  function to_axi_lite_strb(data_width : positive) return std_logic_vector;
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  type axi_lite_m2s_w_t is record
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    valid : std_logic;
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    data : std_logic_vector(axi_lite_data_sz - 1 downto 0);
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    strb : std_logic_vector(axi_lite_w_strb_sz - 1 downto 0);
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  end record;
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5986
  constant axi_lite_m2s_w_init : axi_lite_m2s_w_t := (valid => '0', others => (others => '-'));
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  function axi_lite_m2s_w_sz(data_width : positive) return positive;
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  function to_slv(data : axi_lite_m2s_w_t; data_width : positive) return std_logic_vector;
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  function to_axi_lite_m2s_w(data : std_logic_vector; data_width : positive) return axi_lite_m2s_w_t;
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  type axi_lite_s2m_w_t is record
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    ready : std_logic;
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  end record;
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  constant axi_lite_s2m_w_init : axi_lite_s2m_w_t := (ready => '0');
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  ------------------------------------------------------------------------------
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  -- B (Write Response) channels
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  ------------------------------------------------------------------------------
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  type axi_lite_m2s_b_t is record
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    ready : std_logic;
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  end record;
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  constant axi_lite_m2s_b_init : axi_lite_m2s_b_t := (ready => '0');
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  type axi_lite_s2m_b_t is record
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    valid : std_logic;
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    resp : std_logic_vector(axi_resp_sz - 1 downto 0);
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  end record;
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  constant axi_lite_s2m_b_init : axi_lite_s2m_b_t := (valid => '0', others => (others => '0'));
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  -- Exluded member: valid
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  constant axi_lite_s2m_b_sz : positive := axi_resp_sz;
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  ------------------------------------------------------------------------------
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  -- R (Read Data) channels
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  ------------------------------------------------------------------------------
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  type axi_lite_m2s_r_t is record
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    ready : std_logic;
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  end record;
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  constant axi_lite_m2s_r_init : axi_lite_m2s_r_t := (ready => '0');
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  type axi_lite_s2m_r_t is record
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    valid : std_logic;
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    data : std_logic_vector(axi_lite_data_sz - 1 downto 0);
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    resp : std_logic_vector(axi_resp_sz - 1 downto 0);
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  end record;
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5494
  constant axi_lite_s2m_r_init : axi_lite_s2m_r_t := (valid => '0', others => (others => '0'));
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  function axi_lite_s2m_r_sz(data_width : positive) return positive;
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  function to_slv(data : axi_lite_s2m_r_t; data_width : positive) return std_logic_vector;
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  function to_axi_lite_s2m_r(data : std_logic_vector; data_width : positive) return axi_lite_s2m_r_t;
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  ------------------------------------------------------------------------------
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  -- The complete buses
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  ------------------------------------------------------------------------------
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  type axi_lite_read_m2s_t is record
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    ar : axi_lite_m2s_a_t;
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    r : axi_lite_m2s_r_t;
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  end record;
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  type axi_lite_read_m2s_vec_t is array (integer range <>) of axi_lite_read_m2s_t;
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  constant axi_lite_read_m2s_init : axi_lite_read_m2s_t := (
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    ar => axi_lite_m2s_a_init,
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    r => axi_lite_m2s_r_init
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  );
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  type axi_lite_read_s2m_t is record
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    ar : axi_lite_s2m_a_t;
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    r : axi_lite_s2m_r_t;
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  end record;
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  type axi_lite_read_s2m_vec_t is array (integer range <>) of axi_lite_read_s2m_t;
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  constant axi_lite_read_s2m_init : axi_lite_read_s2m_t := (
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    ar => axi_lite_s2m_a_init,
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    r => axi_lite_s2m_r_init
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  );
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  type axi_lite_write_m2s_t is record
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    aw : axi_lite_m2s_a_t;
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    w : axi_lite_m2s_w_t;
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    b : axi_lite_m2s_b_t;
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  end record;
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  type axi_lite_write_m2s_vec_t is array (integer range <>) of axi_lite_write_m2s_t;
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  constant axi_lite_write_m2s_init : axi_lite_write_m2s_t := (
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    aw => axi_lite_m2s_a_init,
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    w => axi_lite_m2s_w_init,
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    b => axi_lite_m2s_b_init
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  );
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  type axi_lite_write_s2m_t is record
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    aw : axi_lite_s2m_a_t;
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    w : axi_lite_s2m_w_t;
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    b : axi_lite_s2m_b_t;
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  end record;
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  type axi_lite_write_s2m_vec_t is array (integer range <>) of axi_lite_write_s2m_t;
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  constant axi_lite_write_s2m_init : axi_lite_write_s2m_t := (
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    aw => axi_lite_s2m_a_init,
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    w => axi_lite_s2m_w_init,
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    b => axi_lite_s2m_b_init
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  );
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  type axi_lite_m2s_t is record
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    read : axi_lite_read_m2s_t;
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    write : axi_lite_write_m2s_t;
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  end record;
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  type axi_lite_m2s_vec_t is array (integer range <>) of axi_lite_m2s_t;
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  constant axi_lite_m2s_init : axi_lite_m2s_t := (
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    read => axi_lite_read_m2s_init,
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    write => axi_lite_write_m2s_init
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  );
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  type axi_lite_s2m_t is record
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    read : axi_lite_read_s2m_t;
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    write : axi_lite_write_s2m_t;
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  end record;
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  type axi_lite_s2m_vec_t is array (integer range <>) of axi_lite_s2m_t;
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  constant axi_lite_s2m_init : axi_lite_s2m_t := (
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    read => axi_lite_read_s2m_init,
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    write => axi_lite_write_s2m_init
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  );
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end;
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package body axi_lite_pkg is
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  function axi_lite_m2s_a_sz(addr_width : positive) return positive is
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  begin
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    -- Excluded membed: valid.
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16096
    return addr_width;
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  end function;
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  function axi_lite_m2s_w_sz(data_width : positive) return positive is
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  begin
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73950
    assert data_width = 32 or data_width = 64
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      report "AXI4-Lite protocol only supports data width 32 or 64" severity failure;
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    -- Exluded member: valid
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73950
    return data_width + axi_w_strb_width(data_width);
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  end function;
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  function to_axi_lite_strb(data_width : positive) return std_logic_vector is
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    variable result : std_logic_vector(axi_lite_w_strb_sz - 1 downto 0) := (others => '0');
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  begin
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    result(data_width / 8 - 1 downto 0) := (others => '1');
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    return result;
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  end function;
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  function to_slv(data : axi_lite_m2s_w_t; data_width : positive) return std_logic_vector is
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2286222
    variable result : std_logic_vector(axi_lite_m2s_w_sz(data_width) - 1 downto 0);
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57894
    variable lo, hi : natural := 0;
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  begin
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57894
    lo := 0;
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57894
    hi := lo + data_width - 1;
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57894
    result(hi downto lo) := data.data(data_width - 1 downto 0);
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57894
    lo := hi + 1;
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57894
    hi := lo + axi_w_strb_width(data_width) - 1;
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57894
    result(hi downto lo) := data.strb(axi_w_strb_width(data_width) - 1 downto 0);
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57894
    assert hi = result'high severity failure;
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57894
    return result;
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  end function;
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  function to_axi_lite_m2s_w(
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    data : std_logic_vector;
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    data_width : positive
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  ) return axi_lite_m2s_w_t is
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66088
    variable result : axi_lite_m2s_w_t := axi_lite_m2s_w_init;
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66088
    variable lo, hi : natural := 0;
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  begin
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66088
    lo := 0;
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66088
    hi := lo + data_width - 1;
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66088
    result.data(data_width - 1 downto 0) := data(hi downto lo);
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66088
    lo := hi + 1;
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66088
    hi := lo + axi_w_strb_width(data_width) - 1;
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66088
    result.strb(axi_w_strb_width(data_width) - 1 downto 0) := data(hi downto lo);
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66088
    assert hi = data'high severity failure;
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66088
    return result;
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  end function;
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  function axi_lite_s2m_r_sz(data_width : positive)  return positive is
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  begin
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    -- Exluded member: valid
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57860
    return data_width + axi_resp_sz;
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  end function;
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  function to_slv(data : axi_lite_s2m_r_t; data_width : positive) return std_logic_vector is
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1591268
    variable result : std_logic_vector(axi_lite_s2m_r_sz(data_width) - 1 downto 0);
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41804
    variable lo, hi : natural := 0;
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  begin
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41804
    lo := 0;
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41804
    hi := lo + data_width - 1;
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41804
    result(hi downto lo) := data.data(data_width - 1 downto 0);
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41804
    lo := hi + 1;
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41804
    hi := lo + axi_resp_sz - 1;
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41804
    result(hi downto lo) := data.resp;
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41804
    assert hi = result'high severity failure;
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41804
    return result;
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  end function;
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  function to_axi_lite_s2m_r(
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    data : std_logic_vector;
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    data_width : positive
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  ) return axi_lite_s2m_r_t is
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66384
    variable result : axi_lite_s2m_r_t := axi_lite_s2m_r_init;
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66384
    variable lo, hi : natural := 0;
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  begin
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66384
    lo := 0;
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66384
    hi := lo + data_width - 1;
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66384
    result.data(data_width - 1 downto 0) := data(hi downto lo);
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66384
    lo := hi + 1;
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66384
    hi := lo + axi_resp_sz - 1;
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66384
    result.resp := data(hi downto lo);
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66384
    assert hi = data'high severity failure;
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66466
    return result;
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  end function;
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end;