GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_lite_simple_read_crossbar.vhd Lines: 26 26 100.0 %
Date: 2021-06-12 04:12:08 Branches: 135 168 80.4 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Simple N-to-1 crossbar for connecting multiple AXI-Lite masters to one port.
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-- This is a wrapper around the simple AXI read crossbar. See that entity for details.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library axi;
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use axi.axi_pkg.all;
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use axi.axi_lite_pkg.all;
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entity axi_lite_simple_read_crossbar is
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  generic(
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    num_inputs : integer
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  );
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  port(
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    clk : in std_logic;
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    --
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    input_ports_m2s : in axi_lite_read_m2s_vec_t(0 to num_inputs - 1) :=
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      (others => axi_lite_read_m2s_init);
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    input_ports_s2m : out axi_lite_read_s2m_vec_t(0 to num_inputs - 1) :=
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      (others => axi_lite_read_s2m_init);
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    --
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    output_m2s : out axi_lite_read_m2s_t := axi_lite_read_m2s_init;
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    output_s2m : in axi_lite_read_s2m_t := axi_lite_read_s2m_init
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  );
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end entity;
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architecture a of axi_lite_simple_read_crossbar is
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  signal input_ports_axi_m2s : axi_read_m2s_vec_t(0 to num_inputs - 1) :=
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    (others => axi_read_m2s_init);
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  signal input_ports_axi_s2m : axi_read_s2m_vec_t(0 to num_inputs - 1) :=
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    (others => axi_read_s2m_init);
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  signal output_axi_m2s : axi_read_m2s_t := axi_read_m2s_init;
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  signal output_axi_s2m : axi_read_s2m_t := axi_read_s2m_init;
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begin
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  -- Assign to the AXI records only what is needed for the AXI-Lite function.
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  ------------------------------------------------------------------------------
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  input_ports_loop : for input_idx in input_ports_m2s'range generate
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    input_ports_axi_m2s(input_idx).ar.valid <= input_ports_m2s(input_idx).ar.valid;
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    input_ports_axi_m2s(input_idx).ar.addr <= input_ports_m2s(input_idx).ar.addr;
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    input_ports_s2m(input_idx).ar.ready <= input_ports_axi_s2m(input_idx).ar.ready;
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    input_ports_axi_m2s(input_idx).r.ready <= input_ports_m2s(input_idx).r.ready;
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    input_ports_s2m(input_idx).r.valid <= input_ports_axi_s2m(input_idx).r.valid;
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    input_ports_s2m(input_idx).r.data <=
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      input_ports_axi_s2m(input_idx).r.data(input_ports_s2m(input_idx).r.data'range);
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    input_ports_s2m(input_idx).r.resp <=
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      input_ports_axi_s2m(input_idx).r.resp(input_ports_s2m(input_idx).r.resp'range);
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  end generate;
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  output_m2s.ar.valid <= output_axi_m2s.ar.valid;
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  output_m2s.ar.addr <= output_axi_m2s.ar.addr;
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  output_axi_s2m.ar.ready <= output_s2m.ar.ready;
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  output_m2s.r.ready <= output_axi_m2s.r.ready;
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  output_axi_s2m.r.valid <= output_s2m.r.valid;
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  output_axi_s2m.r.data(output_s2m.r.data'range) <= output_s2m.r.data;
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  output_axi_s2m.r.resp(output_s2m.r.resp'range) <= output_s2m.r.resp;
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  -- AXI-Lite always burst length 1. Need to set last for the logic in axi_interconnect.
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  output_axi_s2m.r.last <= '1';
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  ------------------------------------------------------------------------------
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  axi_simple_read_crossbar_inst : entity work.axi_simple_read_crossbar
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    generic map (
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      num_inputs => num_inputs
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    )
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    port map (
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      clk => clk,
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      --
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      input_ports_m2s => input_ports_axi_m2s,
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      input_ports_s2m => input_ports_axi_s2m,
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      --
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      output_m2s => output_axi_m2s,
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      output_s2m => output_axi_s2m
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    );
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end architecture;