GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_lite_simple_write_crossbar.vhd Lines: 29 29 100.0 %
Date: 2021-06-12 04:12:08 Branches: 180 220 81.8 %

Line Branch Exec Source
1
12
-- -------------------------------------------------------------------------------------------------
2
-- Copyright (c) Lukas Vik. All rights reserved.
3
--
4
-- This file is part of the tsfpga project.
5
-- https://tsfpga.com
6
-- https://gitlab.com/tsfpga/tsfpga
7
-- -------------------------------------------------------------------------------------------------
8
-- Simple N-to-1 crossbar for connecting multiple AXI-Lite masters to one port.
9
-- This is a wrapper around the simple AXI write crossbar. See that entity for details.
10
-- -------------------------------------------------------------------------------------------------
11
12
library ieee;
13
use ieee.std_logic_1164.all;
14
15
library axi;
16
use axi.axi_pkg.all;
17
use axi.axi_lite_pkg.all;
18
19
20






4816
entity axi_lite_simple_write_crossbar is
21
  generic(
22
    num_inputs : integer
23
  );
24
  port(
25
    clk : in std_logic;
26
    --
27
    input_ports_m2s : in axi_lite_write_m2s_vec_t(0 to num_inputs - 1) :=
28
      (others => axi_lite_write_m2s_init);
29
    input_ports_s2m : out axi_lite_write_s2m_vec_t(0 to num_inputs - 1) :=
30
      (others => axi_lite_write_s2m_init);
31
    --
32
    output_m2s : out axi_lite_write_m2s_t := axi_lite_write_m2s_init;
33
    output_s2m : in axi_lite_write_s2m_t := axi_lite_write_s2m_init
34
  );
35
end entity;
36
37
10
architecture a of axi_lite_simple_write_crossbar is
38
39
2172
  signal input_ports_axi_m2s : axi_write_m2s_vec_t(0 to num_inputs - 1) :=
40
    (others => axi_write_m2s_init);
41





2396
  signal input_ports_axi_s2m : axi_write_s2m_vec_t(0 to num_inputs - 1) :=
42




442
    (others => axi_write_s2m_init);
43
44








1618
  signal output_axi_m2s : axi_write_m2s_t := axi_write_m2s_init;
45

118
  signal output_axi_s2m : axi_write_s2m_t := axi_write_s2m_init;
46
47
begin
48
49
  -- Assign to the AXI records only what is needed for the AXI-Lite function.
50
51
  ------------------------------------------------------------------------------
52
  input_ports_loop : for input_idx in input_ports_axi_m2s'range generate
53
3035
    input_ports_axi_m2s(input_idx).aw.valid <= input_ports_m2s(input_idx).aw.valid;
54


66487
    input_ports_axi_m2s(input_idx).aw.addr <= input_ports_m2s(input_idx).aw.addr;
55
56


9968
    input_ports_s2m(input_idx).aw.ready <= input_ports_axi_s2m(input_idx).aw.ready;
57
58

2016
    input_ports_axi_m2s(input_idx).w.valid <= input_ports_m2s(input_idx).w.valid;
59


67072
    input_ports_axi_m2s(input_idx).w.data(input_ports_m2s(0).w.data'range) <=
60
      input_ports_m2s(input_idx).w.data;
61


316
    input_ports_axi_m2s(input_idx).w.strb(input_ports_m2s(0).w.strb'range) <=
62
      input_ports_m2s(input_idx).w.strb;
63
64


2016
    input_ports_s2m(input_idx).w.ready <= input_ports_axi_s2m(input_idx).w.ready;
65
66

2016
    input_ports_axi_m2s(input_idx).b.ready <= input_ports_m2s(input_idx).b.ready;
67
68


2016
    input_ports_s2m(input_idx).b.valid <= input_ports_axi_s2m(input_idx).b.valid;
69


114
    input_ports_s2m(input_idx).b.resp <= input_ports_axi_s2m(input_idx).b.resp;
70
  end generate;
71
72

2004
  output_m2s.aw.valid <= output_axi_m2s.aw.valid;
73

130518
  output_m2s.aw.addr <= output_axi_m2s.aw.addr;
74
75

33282
  output_axi_s2m.aw.ready <= output_s2m.aw.ready;
76
77

2004
  output_m2s.w.valid <= output_axi_m2s.w.valid;
78

130388
  output_m2s.w.data <= output_axi_m2s.w.data(output_m2s.w.data'range);
79

18070
  output_m2s.w.strb <= output_axi_m2s.w.strb(output_m2s.w.strb'range);
80
81

2004
  output_axi_s2m.w.ready <= output_s2m.w.ready;
82
83

2004
  output_m2s.b.ready <= output_axi_m2s.b.ready;
84
85

2004
  output_axi_s2m.b.valid <= output_s2m.b.valid;
86

22
  output_axi_s2m.b.resp <= output_s2m.b.resp;
87
88
89
  ------------------------------------------------------------------------------
90
2
  axi_simple_write_crossbar_inst : entity work.axi_simple_write_crossbar
91
    generic map (
92
      num_inputs => num_inputs
93
    )
94
    port map (
95
      clk => clk,
96
      --
97
      input_ports_m2s => input_ports_axi_m2s,
98
      input_ports_s2m => input_ports_axi_s2m,
99
      --
100
      output_m2s => output_axi_m2s,
101
      output_s2m => output_axi_s2m
102
    );
103
104
end architecture;