GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_lite_to_vec.vhd Lines: 21 21 100.0 %
Date: 2021-06-12 04:12:08 Branches: 161 197 81.7 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Convenience wrapper for splitting and CDC'ing a register bus.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library axi;
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use axi.axi_lite_pkg.all;
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library common;
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use common.addr_pkg.all;
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use common.attribute_pkg.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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26585
entity axi_lite_to_vec is
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  generic (
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    axi_lite_slaves : addr_and_mask_vec_t;
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    clocks_are_the_same : boolean_vector(axi_lite_slaves'range) := (others => true);
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    cdc_fifo_depth : positive := 16;
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    cdc_ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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3015
    clk_axi_lite : in std_logic;
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    axi_lite_m2s : in axi_lite_m2s_t;
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    axi_lite_s2m : out axi_lite_s2m_t;
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6015
    -- Only need to set if different from clk_axi_lite
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1044
    clk_axi_lite_vec : in std_logic_vector(axi_lite_slaves'range) := (others => '0');
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    axi_lite_m2s_vec : out axi_lite_m2s_vec_t(axi_lite_slaves'range);
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    axi_lite_s2m_vec : in axi_lite_s2m_vec_t(axi_lite_slaves'range)
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  );
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end entity;
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16178
architecture a of axi_lite_to_vec is
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3590
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  constant addr_width : positive := addr_bits_needed(axi_lite_slaves);
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  signal axi_lite_m2s_vec_int : axi_lite_m2s_vec_t(axi_lite_slaves'range);
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  signal axi_lite_s2m_vec_int : axi_lite_s2m_vec_t(axi_lite_slaves'range);
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begin
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  ------------------------------------------------------------------------------
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  axi_lite_mux_inst : entity axi.axi_lite_mux
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    generic map (
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      slave_addrs => axi_lite_slaves
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    )
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    port map (
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      clk => clk_axi_lite,
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      axi_lite_m2s => axi_lite_m2s,
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      axi_lite_s2m => axi_lite_s2m,
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      axi_lite_m2s_vec => axi_lite_m2s_vec_int,
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      axi_lite_s2m_vec => axi_lite_s2m_vec_int
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    );
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    ------------------------------------------------------------------------------
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    clock_domain_crossing : for slave in axi_lite_slaves'range generate
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      assign : if clocks_are_the_same(slave) generate
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        axi_lite_m2s_vec(slave) <= axi_lite_m2s_vec_int(slave);
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23252
        axi_lite_s2m_vec_int(slave) <= axi_lite_s2m_vec(slave);
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      else generate
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        axi_lite_cdc_inst : entity axi.axi_lite_cdc
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          generic map (
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            data_width => reg_width,
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            addr_width => addr_width,
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            fifo_depth => cdc_fifo_depth,
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            ram_type => cdc_ram_type
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          )
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          port map (
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            clk_master => clk_axi_lite,
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            master_m2s => axi_lite_m2s_vec_int(slave),
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            master_s2m => axi_lite_s2m_vec_int(slave),
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            --
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            clk_slave => clk_axi_lite_vec(slave),
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            slave_m2s => axi_lite_m2s_vec(slave),
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            slave_s2m => axi_lite_s2m_vec(slave)
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          );
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      end generate;
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    end generate;
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end architecture;