GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_stream_fifo.vhd Lines: 21 21 100.0 %
Date: 2021-06-12 04:12:08 Branches: 41 57 71.9 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- FIFO for AXI Stream. Can be used as clock crossing by setting the "asynchronous" generic.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library fifo;
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library common;
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use common.attribute_pkg.all;
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use work.axi_stream_pkg.all;
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entity axi_stream_fifo is
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  generic (
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    data_width : positive;
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    user_width : natural;
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    asynchronous : boolean;
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    depth : positive;
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    ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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    clk : in std_logic;
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    --
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    input_m2s : in axi_stream_m2s_t;
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    input_s2m : out axi_stream_s2m_t := axi_stream_s2m_init;
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    --
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    output_m2s : out axi_stream_m2s_t := axi_stream_m2s_init;
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    output_s2m : in axi_stream_s2m_t;
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    -- Only need to assign the clock if generic asynchronous is "True"
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    clk_output : in std_logic := '0'
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  );
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end entity;
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architecture a of axi_stream_fifo is
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  constant bus_width : integer := axi_stream_m2s_sz(data_width, user_width);
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  signal write_data, read_data : std_logic_vector(bus_width - 1 downto 0);
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  signal read_valid : std_logic := '0';
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begin
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  write_data <= to_slv(input_m2s, data_width, user_width);
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  output_m2s <= to_axi_stream_m2s(
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    data=>read_data,
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    data_width=>data_width,
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    user_width=>user_width,
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    valid=>read_valid
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  );
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  ------------------------------------------------------------------------------
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  fifo_wrapper_inst : entity fifo.fifo_wrapper
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    generic map (
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      use_asynchronous_fifo => asynchronous,
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      width => bus_width,
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      depth => depth,
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      ram_type => ram_type
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    )
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    port map(
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      clk => clk,
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      clk_read => clk_output,
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      clk_write => clk,
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      --
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      read_ready => output_s2m.ready,
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      read_valid => read_valid,
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      read_data => read_data,
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      --
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      write_ready => input_s2m.ready,
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      write_valid => input_m2s.valid,
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      write_data => write_data
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    );
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end architecture;