GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_to_axi_lite.vhd Lines: 52 52 100.0 %
Date: 2021-06-12 04:12:08 Branches: 244 317 77.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Convert AXI transfers to AXI-Lite transfers.
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--
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-- This module does not handle conversion of non-well behaved AXI transfers.
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-- Burst length has to be one and size must be the width of the bus. If these
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-- conditions are not met, the read/write response will signal SLVERR.
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--
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-- This module will throttle the AXI bus so that there is never more that one
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-- outstanding transaction (read and write separate). While the AXI-Lite standard
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-- does allow for outstanding bursts, some Xilinx cores, namely the PCIe DMA bridge
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-- does not play well with it.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library common;
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use common.types_pkg.all;
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library math;
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use math.math_pkg.all;
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use work.axi_pkg.all;
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use work.axi_lite_pkg.all;
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37738
entity axi_to_axi_lite is
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  generic (
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    data_width : integer
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  );
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  port (
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    clk : in std_logic;
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    axi_m2s : in axi_m2s_t := axi_m2s_init;
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    axi_s2m : out axi_s2m_t := axi_s2m_init;
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    axi_lite_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
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    axi_lite_s2m : in axi_lite_s2m_t := axi_lite_s2m_init
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  );
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end entity;
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architecture a of axi_to_axi_lite is
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  constant len : integer := 0;
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  constant size : integer := log2(data_width / 8);
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1843
  signal read_id, write_id : unsigned(axi_m2s.read.ar.id'range) := (others => '0');
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  subtype data_rng is integer range data_width - 1 downto 0;
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  subtype strb_rng is integer range data_width / 8 - 1 downto 0;
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  signal read_error, write_error : boolean := false;
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  signal ar_done, aw_done, w_done : std_logic := '0';
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begin
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  ------------------------------------------------------------------------------
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8687
  axi_lite_m2s.read.ar.valid <= axi_m2s.read.ar.valid and not ar_done;
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143241
  axi_lite_m2s.read.ar.addr <= axi_m2s.read.ar.addr;
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31575
  axi_s2m.read.ar.ready <= axi_lite_s2m.read.ar.ready and not ar_done;
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  axi_lite_m2s.read.r.ready <= axi_m2s.read.r.ready;
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  axi_s2m.read.r.valid <= axi_lite_s2m.read.r.valid;
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1606
  axi_s2m.read.r.id <= read_id;
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107898
  axi_s2m.read.r.data(data_rng) <= axi_lite_s2m.read.r.data(data_rng);
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  axi_s2m.read.r.resp <= axi_resp_slverr when read_error else axi_lite_s2m.read.r.resp;
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  axi_s2m.read.r.last <= '1';
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  ------------------------------------------------------------------------------
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6335
  axi_lite_m2s.write.aw.valid <= axi_m2s.write.aw.valid and not aw_done;
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  axi_lite_m2s.write.aw.addr <= axi_m2s.write.aw.addr;
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  axi_s2m.write.aw.ready <= axi_lite_s2m.write.aw.ready and not aw_done;
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  axi_lite_m2s.write.w.valid <= axi_m2s.write.w.valid and not w_done;
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101595
  axi_lite_m2s.write.w.data(data_rng) <= axi_m2s.write.w.data(data_rng);
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  axi_lite_m2s.write.w.strb(strb_rng) <= axi_m2s.write.w.strb(strb_rng);
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  axi_s2m.write.w.ready <= axi_lite_s2m.write.w.ready and not w_done;
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  ------------------------------------------------------------------------------
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  axi_lite_m2s.write.b.ready <= axi_m2s.write.b.ready;
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4228
  axi_s2m.write.b.valid <= axi_lite_s2m.write.b.valid;
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  axi_s2m.write.b.id <= write_id;
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286113
  axi_s2m.write.b.resp <= axi_resp_slverr when write_error else axi_lite_s2m.write.b.resp;
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  ------------------------------------------------------------------------------
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  mirror_id : process
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  begin
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285616
    wait until rising_edge(clk);
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    -- Save the ID's so they can be returned in the read/write response transaction.
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71403
    if axi_s2m.read.ar.ready and axi_m2s.read.ar.valid then
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      read_id <= axi_m2s.read.ar.id;
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2225
      ar_done <= '1';
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    end if;
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71403
    if axi_m2s.read.r.ready and axi_s2m.read.r.valid then
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2225
      ar_done <= '0';
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    end if;
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71403
    if axi_s2m.write.aw.ready and axi_m2s.write.aw.valid then
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53675
      write_id <= axi_m2s.write.aw.id;
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2147
      aw_done <= '1';
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    end if;
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71403
    if axi_s2m.write.w.ready and axi_m2s.write.w.valid then
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2091
      w_done <= '1';
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    end if;
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71403
    if axi_m2s.write.b.ready and axi_s2m.write.b.valid then
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2147
      aw_done <= '0';
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428422
      w_done <= '0';
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    end if;
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  end process;
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  ------------------------------------------------------------------------------
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  check_for_bus_error : process
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  begin
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285616
    wait until rising_edge(clk);
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    -- If an error occurs the bus will return an error. The bus will be unlocked for any
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    -- upcoming transactions, if the SW can handle it.
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71403
    if axi_m2s.write.aw.valid and axi_s2m.write.aw.ready then
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      if to_integer(unsigned(axi_m2s.write.aw.len)) /= len or to_integer(unsigned(axi_m2s.write.aw.size)) /= size then
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        write_error <= true;
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      else
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        write_error <= false;
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      end if;
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    end if;
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71403
    if axi_m2s.read.ar.valid and axi_s2m.read.ar.ready then
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      if to_integer(unsigned(axi_m2s.read.ar.len)) /= len or to_integer(unsigned(axi_m2s.read.ar.size)) /= size then
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        read_error <= true;
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      else
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142825
        read_error <= false;
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      end if;
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    end if;
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  end process;
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end architecture;