GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_to_axi_lite_vec.vhd Lines: 21 21 100.0 %
Date: 2021-06-12 04:12:08 Branches: 209 231 90.5 %

Line Branch Exec Source
1
54
-- -------------------------------------------------------------------------------------------------
2
-- Copyright (c) Lukas Vik. All rights reserved.
3
--
4
-- This file is part of the tsfpga project.
5
-- https://tsfpga.com
6
-- https://gitlab.com/tsfpga/tsfpga
7
-- -------------------------------------------------------------------------------------------------
8
-- Convenience wrapper for splitting and CDC'ing a register bus.
9
-- -------------------------------------------------------------------------------------------------
10
11
library ieee;
12
use ieee.std_logic_1164.all;
13
14
library common;
15
use common.addr_pkg.all;
16
17
library axi;
18
use axi.axi_pkg.all;
19
use axi.axi_lite_pkg.all;
20
21
22















31661
entity axi_to_axi_lite_vec is
23
  generic (
24
    axi_lite_slaves : addr_and_mask_vec_t;
25
    clocks_are_the_same : boolean_vector(axi_lite_slaves'range) := (others => true);
26
    pipeline : boolean := false;
27
    -- Only needed if pipeline is enabled
28
1
    data_width : positive := 32
29
  );
30


201
  port (
31



137
    clk_axi : in std_logic;
32
    axi_m2s : in axi_m2s_t;
33




401
    axi_s2m : out axi_s2m_t;
34
1878
35



1233
    -- Only need to set if different from axi_clk
36
    clk_axi_lite_vec : in std_logic_vector(axi_lite_slaves'range) := (others => '0');
37
    axi_lite_m2s_vec : out axi_lite_m2s_vec_t(axi_lite_slaves'range);
38

89
    axi_lite_s2m_vec : in axi_lite_s2m_vec_t(axi_lite_slaves'range)
39





16098
  );
40


2778
end entity;
41
3339
42
3258
architecture a of axi_to_axi_lite_vec is
43
44
7218
  signal axi_lite_m2s, axi_lite_pipelined_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
45
1855
  signal axi_lite_s2m, axi_lite_pipelined_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
46
47
9
  constant addr_width : positive := addr_bits_needed(axi_lite_slaves);
48
49
begin
50
51
  ------------------------------------------------------------------------------
52
9
  axi_to_axi_lite_inst : entity work.axi_to_axi_lite
53
    generic map (
54
      data_width => 32
55
    )
56
    port map (
57
      clk => clk_axi,
58
59
      axi_m2s => axi_m2s,
60
      axi_s2m => axi_s2m,
61
62
      axi_lite_m2s => axi_lite_m2s,
63
      axi_lite_s2m => axi_lite_s2m
64
    );
65
66
67
  ------------------------------------------------------------------------------
68
  pipeline_gen : if pipeline generate
69
10
    axi_lite_pipeline_inst : entity work.axi_lite_pipeline
70
      generic map (
71
        data_width => data_width,
72
        addr_width => addr_width
73
      )
74
      port map (
75
        clk => clk_axi,
76
        --
77
        master_m2s => axi_lite_m2s,
78
        master_s2m => axi_lite_s2m,
79
        --
80
        slave_m2s => axi_lite_pipelined_m2s,
81
        slave_s2m => axi_lite_pipelined_s2m
82
      );
83
84
  else generate
85











113374
    axi_lite_pipelined_m2s <= axi_lite_m2s;
86









35458
    axi_lite_s2m <= axi_lite_pipelined_s2m;
87
88
  end generate;
89
90
  ------------------------------------------------------------------------------
91
9
  axi_lite_to_vec_inst : entity work.axi_lite_to_vec
92
    generic map (
93
      axi_lite_slaves => axi_lite_slaves,
94
      clocks_are_the_same => clocks_are_the_same
95
    )
96
    port map (
97
      clk_axi_lite => clk_axi,
98
      axi_lite_m2s => axi_lite_pipelined_m2s,
99
      axi_lite_s2m => axi_lite_pipelined_s2m,
100
101
      clk_axi_lite_vec => clk_axi_lite_vec,
102
      axi_lite_m2s_vec => axi_lite_m2s_vec,
103
      axi_lite_s2m_vec => axi_lite_s2m_vec
104
    );
105
106
end architecture;