GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_w_fifo.vhd Lines: 24 24 100.0 %
Date: 2021-06-12 04:12:08 Branches: 68 92 73.9 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- FIFO for AXI write data channel (W). Can be used as clock crossing by setting
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-- the "asynchronous" generic.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library common;
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use common.attribute_pkg.all;
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library fifo;
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use work.axi_pkg.all;
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52975
entity axi_w_fifo is
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  generic (
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    asynchronous : boolean;
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    data_width : positive;
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    depth : natural;
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    enable_packet_mode : boolean := false;
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    ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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    clk : in std_logic;
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    --
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    input_m2s : in axi_m2s_w_t;
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    input_s2m : out axi_s2m_w_t := axi_s2m_w_init;
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    --
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    output_m2s : out axi_m2s_w_t := axi_m2s_w_init;
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    output_s2m : in axi_s2m_w_t;
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    -- Level of the FIFO. If this is an asynchronous FIFO, this value is on the "output" side.
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    output_level : out integer range 0 to depth := 0;
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    -- Only needs to assign the clock if generic asynchronous is "True"
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1120
    clk_input : in std_logic := '0'
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  );
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end entity;
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architecture a of axi_w_fifo is
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begin
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  passthrough_or_fifo : if depth = 0 generate
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4955082
    output_m2s <= input_m2s;
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    input_s2m <= output_s2m;
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  else generate
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    constant w_width : integer := axi_m2s_w_sz(data_width);
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    signal read_valid : std_logic := '0';
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    signal read_data, write_data : std_logic_vector(w_width - 1 downto 0);
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  begin
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    ------------------------------------------------------------------------------
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    assign : process(all)
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    begin
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      output_m2s <= to_axi_m2s_w(read_data, data_width);
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      output_m2s.valid <= read_valid;
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      write_data <= to_slv(input_m2s, data_width);
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    end process;
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    ------------------------------------------------------------------------------
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    fifo_wrapper_inst : entity fifo.fifo_wrapper
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      generic map (
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        use_asynchronous_fifo => asynchronous,
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        width => w_width,
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        depth => depth,
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        enable_last => enable_packet_mode,
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        enable_packet_mode => enable_packet_mode,
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        ram_type => ram_type
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      )
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      port map(
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        clk => clk,
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        clk_read => clk,
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        clk_write => clk_input,
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        --
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        read_ready => output_s2m.ready,
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        read_valid => read_valid,
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        read_data => read_data,
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        read_level => output_level,
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        --
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        write_ready => input_s2m.ready,
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        write_valid => input_m2s.valid,
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        write_data => write_data,
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        write_last => input_m2s.last
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      );
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  end generate;
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end architecture;