GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/axi_write_cdc.vhd Lines: 17 17 100.0 %
Date: 2021-06-12 04:12:08 Branches: 78 84 92.9 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Clock domain crossing for an AXI write bus.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library common;
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use common.attribute_pkg.all;
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library fifo;
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use work.axi_pkg.all;
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entity axi_write_cdc is
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  generic (
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    id_width : natural;
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    addr_width : positive;
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    data_width : positive;
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    enable_data_fifo_packet_mode : boolean;
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    address_fifo_depth : positive;
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    address_fifo_ram_type : ram_style_t := ram_style_auto;
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    data_fifo_depth : positive;
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    data_fifo_ram_type : ram_style_t := ram_style_auto;
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    response_fifo_depth : positive;
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    response_fifo_ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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    clk_input : in std_logic;
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    input_m2s : in axi_write_m2s_t;
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    input_s2m : out axi_write_s2m_t := axi_write_s2m_init;
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    --
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    clk_output : in std_logic;
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    output_m2s : out axi_write_m2s_t := axi_write_m2s_init;
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    output_s2m : in axi_write_s2m_t;
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    output_data_fifo_level : out integer range 0 to data_fifo_depth := 0
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  );
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end entity;
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architecture a of axi_write_cdc is
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begin
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  ------------------------------------------------------------------------------
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  axi_address_fifo_inst : entity work.axi_address_fifo
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    generic map (
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      id_width => id_width,
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      addr_width => addr_width,
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      asynchronous => true,
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      depth => address_fifo_depth,
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      ram_type => address_fifo_ram_type
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_m2s.aw,
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      input_s2m => input_s2m.aw,
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      --
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      output_m2s => output_m2s.aw,
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      output_s2m => output_s2m.aw,
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      --
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      clk_input => clk_input
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    );
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  ------------------------------------------------------------------------------
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  axi_w_fifo_inst : entity work.axi_w_fifo
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    generic map (
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      data_width => data_width,
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      asynchronous => true,
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      enable_packet_mode => enable_data_fifo_packet_mode,
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      depth => data_fifo_depth,
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      ram_type => data_fifo_ram_type
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_m2s.w,
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      input_s2m => input_s2m.w,
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      --
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      output_m2s => output_m2s.w,
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      output_s2m => output_s2m.w,
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      output_level => output_data_fifo_level,
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      --
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      clk_input => clk_input
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    );
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  ------------------------------------------------------------------------------
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  axi_b_fifo_inst : entity work.axi_b_fifo
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    generic map (
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      id_width => id_width,
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      asynchronous => true,
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      depth => response_fifo_depth,
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      ram_type => response_fifo_ram_type
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_m2s.b,
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      input_s2m => input_s2m.b,
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      --
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      output_m2s => output_m2s.b,
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      output_s2m => output_s2m.b,
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      --
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      clk_input => clk_input
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    );
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end architecture;