GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_cdc.vhd Lines: 71 71 100.0 %
Date: 2021-06-12 04:12:08 Branches: 390 463 84.2 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Test AXI clock domain crossing by running transactions through a
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-- axi_read/write_cdc -> axi_read/write_throttle chain. The tests run are not very exhaustive,
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-- it is more of a connectivity test.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.memory_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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library bfm;
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use work.axi_pkg.all;
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197048
entity tb_axi_cdc is
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  generic (
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1542
    input_clk_fast : boolean := false;
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3474
    output_clk_fast : boolean := false;
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3558
    max_burst_length_beats : positive;
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774
    runner_cfg : string
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1854
  );
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1620
end entity;
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1224
architecture tb of tb_axi_cdc is
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930
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3246
  constant id_width : natural := 5;
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168
  constant addr_width : positive := 24;
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  constant data_width : positive := 32;
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6
  constant num_words : positive := 1000;
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  constant clk_fast_period : time := 3 ns;
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6
  constant clk_slow_period : time := 7 ns;
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12
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  signal clk_input, clk_output : std_logic := '0';
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  signal input_read_m2s : axi_read_m2s_t := axi_read_m2s_init;
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3162
  signal input_read_s2m : axi_read_s2m_t := axi_read_s2m_init;
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2172
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1620
  signal input_write_m2s : axi_write_m2s_t := axi_write_m2s_init;
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4614
  signal input_write_s2m : axi_write_s2m_t := axi_write_s2m_init;
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1116
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  constant axi_master : bus_master_t := new_bus(
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    data_length => data_width,
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    address_length => input_read_m2s.ar.addr'length
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  );
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  constant memory : memory_t := new_memory;
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  constant axi_slave : axi_slave_t := new_axi_slave(
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    memory => memory,
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    address_fifo_depth => 4,
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    write_response_fifo_depth => 4,
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    address_stall_probability => 0.3,
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    data_stall_probability => 0.3,
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    write_response_stall_probability => 0.3,
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    min_response_latency => 8 * clk_fast_period,
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    max_response_latency => 16 * clk_slow_period,
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    logger => get_logger("axi_slave")
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  );
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begin
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  clk_input_gen : if input_clk_fast generate
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379254
    clk_input <= not clk_input after clk_fast_period / 2;
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  else generate
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182258
    clk_input <= not clk_input after clk_slow_period / 2;
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  end generate;
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  clk_output_gen : if output_clk_fast generate
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186032
    clk_output <= not clk_output after clk_fast_period / 2;
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  else generate
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186970
    clk_output <= not clk_output after clk_slow_period / 2;
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  end generate;
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42132
  test_runner_watchdog(runner, 1 ms);
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  ------------------------------------------------------------------------------
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6
  main : process
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6
    variable rnd : RandomPType;
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    variable data : std_logic_vector(data_width - 1 downto 0);
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    variable address : integer;
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    variable buf : buffer_t;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    buf := allocate(memory, 4 * num_words);
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    if run("test_read") then
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      for idx in 0 to num_words - 1 loop
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3000
        address := 4 * idx;
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3000
        data := rnd.RandSlv(data'length);
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6000
        write_word(memory, address, data);
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18006
        check_bus(net, axi_master, address, data);
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      end loop;
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    elsif run("test_write") then
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3
      for idx in 0 to num_words - 1 loop
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3000
        address := 4 * idx;
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3000
        data := rnd.RandSlv(data'length);
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6000
        set_expected_word(memory, address, data);
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12003
        write_bus(net, axi_master, address, data);
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      end loop;
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      wait_until_idle(net, as_sync(axi_master));
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      check_expected_was_written(memory);
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    end if;
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36072
    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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6
  axi_master_inst : entity bfm.axi_master
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    generic map (
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      bus_handle => axi_master
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    )
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    port map (
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      clk => clk_input,
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      --
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      axi_read_m2s => input_read_m2s,
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      axi_read_s2m => input_read_s2m,
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      --
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      axi_write_m2s => input_write_m2s,
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      axi_write_s2m => input_write_s2m
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    );
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  ------------------------------------------------------------------------------
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  read_block : block
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1218
    signal resynced_m2s, throttled_m2s : axi_read_m2s_t := axi_read_m2s_init;
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1854
    signal resynced_s2m, throttled_s2m : axi_read_s2m_t := axi_read_s2m_init;
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    constant data_fifo_depth : positive := 1024;
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    signal data_fifo_level : integer range 0 to data_fifo_depth := 0;
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  begin
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    ------------------------------------------------------------------------------
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    axi_read_cdc_inst : entity work.axi_read_cdc
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      generic map (
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        id_width => id_width,
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        addr_width => addr_width,
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        data_width => data_width,
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        enable_data_fifo_packet_mode => false,
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        data_fifo_depth => data_fifo_depth,
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        address_fifo_depth => 32
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      )
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      port map (
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        clk_input => clk_input,
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        input_m2s => input_read_m2s,
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        input_s2m => input_read_s2m,
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        --
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        clk_output => clk_output,
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        output_m2s => resynced_m2s,
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        output_s2m => resynced_s2m,
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        output_data_fifo_level => data_fifo_level
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      );
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    ------------------------------------------------------------------------------
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    axi_read_throttle_inst : entity work.axi_read_throttle
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      generic map (
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        data_fifo_depth => data_fifo_depth,
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        max_burst_length_beats => max_burst_length_beats,
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        id_width => id_width,
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        addr_width => addr_width,
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        full_ar_throughput => false
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      )
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      port map (
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        clk => clk_output,
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        --
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        data_fifo_level => data_fifo_level,
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        --
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        input_m2s => resynced_m2s,
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        input_s2m => resynced_s2m,
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        --
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        throttled_m2s => throttled_m2s,
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        throttled_s2m => throttled_s2m
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      );
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    ------------------------------------------------------------------------------
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    axi_read_slave_wrapper_inst : entity bfm.axi_read_slave
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      generic map (
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        axi_slave => axi_slave,
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        data_width => data_width,
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        id_width => id_width
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      )
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      port map (
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        clk => clk_output,
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        --
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        axi_read_m2s => throttled_m2s,
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        axi_read_s2m => throttled_s2m
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      );
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  end block;
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  ------------------------------------------------------------------------------
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  write_block : block
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3234
    signal resynced_m2s, throttled_m2s : axi_write_m2s_t := axi_write_m2s_init;
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    signal resynced_s2m, throttled_s2m : axi_write_s2m_t := axi_write_s2m_init;
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    constant data_fifo_depth : positive := 1024;
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    signal data_fifo_level : integer range 0 to data_fifo_depth := 0;
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  begin
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    ------------------------------------------------------------------------------
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    axi_write_cdc_inst : entity work.axi_write_cdc
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      generic map (
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        id_width => id_width,
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        addr_width => addr_width,
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        data_width => data_width,
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        enable_data_fifo_packet_mode => true,
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        address_fifo_depth => 32,
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        data_fifo_depth => data_fifo_depth,
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        response_fifo_depth => 32
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      )
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      port map (
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        clk_input => clk_input,
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        input_m2s => input_write_m2s,
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        input_s2m => input_write_s2m,
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        --
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        clk_output => clk_output,
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        output_m2s => resynced_m2s,
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        output_s2m => resynced_s2m,
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        output_data_fifo_level => data_fifo_level
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      );
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    ------------------------------------------------------------------------------
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    axi_write_throttle_inst : entity work.axi_write_throttle
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      generic map (
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        data_fifo_depth => data_fifo_depth,
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        max_burst_length_beats => max_burst_length_beats,
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        id_width => id_width,
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        addr_width => addr_width,
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        full_aw_throughput => false
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      )
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      port map (
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        clk => clk_output,
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        --
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        data_fifo_level => data_fifo_level,
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        --
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        input_m2s => resynced_m2s,
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        input_s2m => resynced_s2m,
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        --
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        throttled_m2s => throttled_m2s,
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        throttled_s2m => throttled_s2m
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      );
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    ------------------------------------------------------------------------------
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    axi_write_slave_wrapper_inst : entity bfm.axi_write_slave
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      generic map (
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        axi_slave => axi_slave,
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        data_width => data_width,
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        id_width => id_width
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      )
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      port map (
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        clk => clk_output,
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        --
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        axi_write_m2s => throttled_m2s,
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        axi_write_s2m => throttled_s2m
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      );
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  end block;
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end architecture;