GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_fifo.vhd Lines: 57 57 100.0 %
Date: 2021-06-12 04:12:08 Branches: 296 368 80.4 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.memory_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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library bfm;
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use work.axi_pkg.all;
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entity tb_axi_fifo is
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  generic (
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    depth : natural;
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    asynchronous : boolean := false;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_fifo is
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180
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1866
  constant data_width : integer := 32;
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4626
  constant id_width : integer := 5;
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  constant num_words : integer := 1000;
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2796
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  constant clk_fast_period : time := 3 ns;
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  constant clk_slow_period : time := 7 ns;
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  signal clk_input, clk_output : std_logic := '0';
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  signal input_read_m2s, output_read_m2s : axi_read_m2s_t := axi_read_m2s_init;
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  signal input_read_s2m, output_read_s2m : axi_read_s2m_t := axi_read_s2m_init;
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  signal input_write_m2s, output_write_m2s : axi_write_m2s_t := axi_write_m2s_init;
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  signal input_write_s2m, output_write_s2m : axi_write_s2m_t := axi_write_s2m_init;
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  constant axi_master : bus_master_t := new_bus(
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    data_length => data_width,
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    address_length => input_read_m2s.ar.addr'length
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  );
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  constant memory : memory_t := new_memory;
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  constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
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    memory => memory,
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    address_fifo_depth => 4,
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    write_response_fifo_depth => 4,
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    address_stall_probability => 0.3,
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    data_stall_probability => 0.3,
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    write_response_stall_probability => 0.3,
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    min_response_latency => 8 * clk_fast_period,
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    max_response_latency => 16 * clk_slow_period,
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    logger => get_logger("axi_slave")
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  );
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begin
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186968
  test_runner_watchdog(runner, 1 ms);
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  clk_input_gen : if asynchronous generate
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186934
    clk_input <= not clk_input after clk_fast_period / 2;
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80114
    clk_output <= not clk_output after clk_slow_period / 2;
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  else generate
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236448
    clk_input <= not clk_input after clk_fast_period / 2;
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    clk_output <= not clk_output after clk_fast_period / 2;
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  end generate;
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  ------------------------------------------------------------------------------
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  main : process
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    variable rnd : RandomPType;
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    variable data : std_logic_vector(data_width - 1 downto 0);
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    variable address : integer;
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    variable buf : buffer_t;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    buf := allocate(memory, 4 * num_words);
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    if run("test_read") then
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      for idx in 0 to num_words - 1 loop
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        address := 4 * idx;
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        data := rnd.RandSlv(data'length);
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        write_word(memory, address, data);
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        check_bus(net, axi_master, address, data);
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      end loop;
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    elsif run("test_write") then
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      for idx in 0 to num_words - 1 loop
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        address := 4 * idx;
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        data := rnd.RandSlv(data'length);
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        set_expected_word(memory, address, data);
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        write_bus(net, axi_master, address, data);
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      end loop;
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      wait_until_idle(net, as_sync(axi_master));
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      check_expected_was_written(memory);
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  axi_input_inst : entity bfm.axi_master
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    generic map (
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      bus_handle => axi_master
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    )
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    port map (
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      clk => clk_input,
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      --
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      axi_read_m2s => input_read_m2s,
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      axi_read_s2m => input_read_s2m,
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      --
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      axi_write_m2s => input_write_m2s,
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      axi_write_s2m => input_write_s2m
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    );
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  ------------------------------------------------------------------------------
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  axi_output_inst : entity bfm.axi_slave
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  generic map (
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    axi_read_slave => axi_read_slave,
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    axi_write_slave => axi_write_slave,
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    data_width => data_width,
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    id_width => id_width
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  )
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  port map (
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    clk => clk_output,
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    --
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    axi_read_m2s => output_read_m2s,
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    axi_read_s2m => output_read_s2m,
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    --
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    axi_write_m2s => output_write_m2s,
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    axi_write_s2m => output_write_s2m
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  );
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  ------------------------------------------------------------------------------
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  axi_ar_fifo_inst : entity work.axi_address_fifo
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    generic map (
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      id_width => id_width,
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      addr_width => 32,
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      asynchronous => asynchronous,
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      depth => depth
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_read_m2s.ar,
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      input_s2m => input_read_s2m.ar,
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      --
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      output_m2s => output_read_m2s.ar,
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      output_s2m => output_read_s2m.ar,
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      --
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      clk_input => clk_input
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    );
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  ------------------------------------------------------------------------------
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  axi_r_fifo_inst : entity work.axi_r_fifo
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    generic map (
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      id_width => id_width,
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      data_width => data_width,
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      asynchronous => asynchronous,
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      depth => depth
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_read_m2s.r,
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      input_s2m => input_read_s2m.r,
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      --
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      output_m2s => output_read_m2s.r,
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      output_s2m => output_read_s2m.r,
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      --
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      clk_input => clk_input
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    );
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  ------------------------------------------------------------------------------
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  axi_aw_fifo_inst : entity work.axi_address_fifo
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    generic map (
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      id_width => id_width,
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      addr_width => 32,
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      asynchronous => asynchronous,
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      depth => depth
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_write_m2s.aw,
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      input_s2m => input_write_s2m.aw,
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      --
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      output_m2s => output_write_m2s.aw,
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      output_s2m => output_write_s2m.aw,
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      --
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      clk_input => clk_input
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    );
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  ------------------------------------------------------------------------------
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  axi_w_fifo_inst : entity work.axi_w_fifo
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    generic map (
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      data_width => data_width,
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      asynchronous => asynchronous,
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      depth => depth
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_write_m2s.w,
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      input_s2m => input_write_s2m.w,
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      --
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      output_m2s => output_write_m2s.w,
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      output_s2m => output_write_s2m.w,
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      --
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      clk_input => clk_input
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    );
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  ------------------------------------------------------------------------------
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  axi_b_fifo_inst : entity work.axi_b_fifo
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    generic map (
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      id_width => id_width,
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      asynchronous => asynchronous,
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      depth => depth
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    )
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    port map (
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      clk => clk_output,
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      --
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      input_m2s => input_write_m2s.b,
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      input_s2m => input_write_s2m.b,
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      --
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      output_m2s => output_write_m2s.b,
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      output_s2m => output_write_s2m.b,
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      --
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      clk_input => clk_input
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    );
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end architecture;