GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_lite_cdc.vhd Lines: 47 47 100.0 %
Date: 2021-06-12 04:12:08 Branches: 163 232 70.3 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.memory_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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library bfm;
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use work.axi_pkg.all;
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use work.axi_lite_pkg.all;
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entity tb_axi_lite_cdc is
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  generic (
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    master_clk_fast : boolean := false;
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    slave_clk_fast : boolean := false;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_lite_cdc is
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  constant data_width : integer := 32;
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  constant addr_width : integer := 24;
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  constant num_words : integer := 2048;
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  constant clk_fast_period : time := 3 ns;
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  constant clk_slow_period : time := 7 ns;
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  signal clk_master, clk_slave : std_logic := '0';
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  signal master_m2s, slave_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
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  signal master_s2m, slave_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
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  constant axi_lite_master : bus_master_t := new_bus(
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    data_length => data_width,
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     address_length => master_m2s.read.ar.addr'length
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    );
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  constant memory : memory_t := new_memory;
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  constant axi_lite_read_slave, axi_lite_write_slave : axi_slave_t := new_axi_slave(
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    memory => memory,
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    address_fifo_depth => 8,
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    write_response_fifo_depth => 8,
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    address_stall_probability => 0.3,
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    data_stall_probability => 0.3,
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    write_response_stall_probability => 0.3,
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    min_response_latency => 8 * clk_fast_period,
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    max_response_latency => 16 * clk_slow_period,
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    logger => get_logger("axi_lite_slave_slave")
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  );
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begin
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  test_runner_watchdog(runner, 1 ms);
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  clk_master_gen : if master_clk_fast generate
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    clk_master <= not clk_master after clk_fast_period / 2;
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  else generate
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    clk_master <= not clk_master after clk_slow_period / 2;
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  end generate;
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  clk_slave_gen : if slave_clk_fast generate
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    clk_slave <= not clk_slave after clk_fast_period / 2;
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  else generate
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    clk_slave <= not clk_slave after clk_slow_period / 2;
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  end generate;
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  ------------------------------------------------------------------------------
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  main : process
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    variable rnd : RandomPType;
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    variable data : std_logic_vector(data_width - 1 downto 0);
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    variable address : integer;
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    variable buf : buffer_t;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    buf := allocate(memory, 4 * num_words);
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    for idx in 0 to num_words - 1 loop
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      address := 4 * idx;
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      data := rnd.RandSlv(data'length);
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       -- Call is non-blocking. I.e. we will build up a queue of writes.
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      write_bus(net, axi_lite_master, address, data);
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      set_expected_word(memory, address, data);
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      wait until rising_edge(clk_master);
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    end loop;
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    for idx in 0 to num_words - 1 loop
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      address := 4 * idx;
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      data := read_word(memory, address, 4);
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      check_bus(net, axi_lite_master, address, data);
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    end loop;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  axi_lite_master_inst : entity bfm.axi_lite_master
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    generic map (
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      bus_handle => axi_lite_master
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    )
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    port map (
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      clk => clk_master,
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      axi_lite_m2s => master_m2s,
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      axi_lite_s2m => master_s2m
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    );
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  ------------------------------------------------------------------------------
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  axi_lite_slave_inst : entity bfm.axi_lite_slave
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    generic map (
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      axi_read_slave => axi_lite_read_slave,
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      axi_write_slave => axi_lite_write_slave,
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      data_width => data_width
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    )
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    port map (
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      clk => clk_slave,
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      --
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      axi_lite_read_m2s => slave_m2s.read,
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      axi_lite_read_s2m => slave_s2m.read,
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      --
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      axi_lite_write_m2s => slave_m2s.write,
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      axi_lite_write_s2m => slave_s2m.write
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    );
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  ------------------------------------------------------------------------------
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  dut : entity work.axi_lite_cdc
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    generic map (
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      data_width => data_width,
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      addr_width => addr_width
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    )
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    port map (
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      clk_master => clk_master,
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      master_m2s => master_m2s,
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      master_s2m => master_s2m,
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      clk_slave => clk_slave,
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      slave_m2s => slave_m2s,
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      slave_s2m => slave_s2m
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    );
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end architecture;