GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_lite_pkg.vhd Lines: 33 33 100.0 %
Date: 2021-06-12 04:12:08 Branches: 67 111 60.4 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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use work.axi_lite_pkg.all;
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4036
entity tb_axi_lite_pkg is
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  generic (
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    data_width : positive;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_lite_pkg is
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begin
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  main : process
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    variable rnd : RandomPType;
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24024
    procedure test_slv_conversion(addr_width : positive) is
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260260
      variable data_a : axi_lite_m2s_a_t;
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292292
      variable data_a_slv, data_a_converted : std_logic_vector(axi_lite_m2s_a_sz(addr_width) - 1 downto 0) := (others => '0');
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4004
      variable data_w : axi_lite_m2s_w_t := axi_lite_m2s_w_init;
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436436
      variable data_w_slv, data_w_converted : std_logic_vector(axi_lite_m2s_w_sz(data_width) - 1 downto 0);
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4004
      variable data_r : axi_lite_s2m_r_t := axi_lite_s2m_r_init;
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404404
      variable data_r_slv, data_r_converted : std_logic_vector(axi_lite_s2m_r_sz(data_width) - 1 downto 0);
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    begin
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4004
      data_w_slv := rnd.RandSLV(data_w_slv'length);
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4004
      data_w := to_axi_lite_m2s_w(data_w_slv, data_width);
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4004
      data_w_converted := to_slv(data_w, data_width);
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8008
      check_equal(data_w_converted, data_w_slv, line_num => 50, file_name => "tb_axi_lite_pkg.vhd");
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4004
      data_r_slv := rnd.RandSLV(data_r_slv'length);
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4004
      data_r := to_axi_lite_s2m_r(data_r_slv, data_width);
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4004
      data_r_converted := to_slv(data_r, data_width);
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24026
      check_equal(data_r_converted, data_r_slv, line_num => 56, file_name => "tb_axi_lite_pkg.vhd");
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    end procedure;
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    procedure test_axi_lite_strb is
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2
      constant got : std_logic_vector(axi_lite_w_strb_sz - 1 downto 0) :=
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        to_axi_lite_strb(data_width);
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2
      constant expected : positive := 2 ** (data_width / 8) - 1;
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    begin
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12062
      check_equal(unsigned(got), expected, line_num => 64, file_name => "tb_axi_lite_pkg.vhd");
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    if run("test_slv_conversion") then
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      -- Loop a couple of times to get good random coverage
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2
      for i in 0 to 1000 loop
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4004
        test_slv_conversion(addr_width=>32);
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8010
        test_slv_conversion(addr_width=>40);
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      end loop;
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    elsif run("test_axi_lite_strb") then
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      test_axi_lite_strb;
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    end if;
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12054
    test_runner_cleanup(runner);
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  end process;
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end architecture;