GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_stream_fifo.vhd Lines: 38 38 100.0 %
Date: 2021-06-12 04:12:08 Branches: 102 180 56.7 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.memory_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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use work.axi_stream_pkg.all;
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entity tb_axi_stream_fifo is
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  generic (
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    depth : natural;
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    asynchronous : boolean := false;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_stream_fifo is
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  constant data_width : integer := 32;
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  constant user_width : integer := 16;
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  constant clk_fast_period : time := 3 ns;
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  constant clk_slow_period : time := 7 ns;
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  signal clk_input, clk_output : std_logic := '0';
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  signal input_m2s, output_m2s : axi_stream_m2s_t := axi_stream_m2s_init;
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  signal input_s2m, output_s2m : axi_stream_s2m_t := axi_stream_s2m_init;
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begin
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  test_runner_watchdog(runner, 1 ms);
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  clk_input_gen : if asynchronous generate
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    clk_input <= not clk_input after clk_slow_period / 2;
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    clk_output <= not clk_output after clk_fast_period / 2;
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  else generate
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    clk_input <= not clk_input after clk_fast_period / 2;
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    clk_output <= not clk_output after clk_fast_period / 2;
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  end generate;
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  ------------------------------------------------------------------------------
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  main : process
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    variable rnd : RandomPType;
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    variable data : std_logic_vector(data_width - 1 downto 0);
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    variable user : std_logic_vector(user_width - 1 downto 0);
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    if run("test_single_transaction") then
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      data := rnd.RandSlv(data'length);
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      user := rnd.RandSlv(user'length);
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      input_m2s.data(data'range) <= data;
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      input_m2s.user(user'range) <= user;
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      input_m2s.valid <= '1';
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      wait until rising_edge(clk_input) and input_s2m.ready = '1';
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      input_m2s.valid <= '0';
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      output_s2m.ready <= '1';
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      wait until rising_edge(clk_output) and output_m2s.valid = '1';
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      check_equal(output_m2s.data(data'range), data, line_num => 79, file_name => "tb_axi_stream_fifo.vhd");
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      check_equal(output_m2s.user(user'range), user, line_num => 80, file_name => "tb_axi_stream_fifo.vhd");
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  axi_stream_fifo_inst : entity work.axi_stream_fifo
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    generic map (
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      data_width => data_width,
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      user_width => user_width,
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      asynchronous => asynchronous,
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      depth => depth
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    )
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    port map (
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      clk => clk_input,
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      --
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      input_m2s => input_m2s,
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      input_s2m => input_s2m,
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      --
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      output_m2s => output_m2s,
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      output_s2m => output_s2m,
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      --
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      clk_output => clk_output
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    );
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end architecture;