GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_to_axi_lite.vhd Lines: 41 41 100.0 %
Date: 2021-06-12 04:12:08 Branches: 247 317 77.9 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.memory_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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library bfm;
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use work.axi_pkg.all;
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use work.axi_lite_pkg.all;
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entity tb_axi_to_axi_lite is
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  generic (
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    data_width : integer;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_to_axi_lite is
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  signal clk : std_logic := '0';
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  constant clk_period : time := 10 ns;
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  signal axi_m2s : axi_m2s_t;
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  signal axi_s2m : axi_s2m_t;
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  signal axi_lite_m2s : axi_lite_m2s_t;
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  signal axi_lite_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
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  constant memory : memory_t := new_memory;
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  constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
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    memory => memory,
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    address_fifo_depth => 8,
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    write_response_fifo_depth => 8,
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    address_stall_probability => 0.3,
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    data_stall_probability => 0.3,
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    write_response_stall_probability => 0.3,
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    min_response_latency => 8 * clk_period,
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    max_response_latency => 16 * clk_period,
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    logger => get_logger("axi_slave")
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  );
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  constant axi_master : bus_master_t := new_bus(
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    data_length => data_width,
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    address_length => axi_m2s.read.ar.addr'length
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  );
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begin
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  test_runner_watchdog(runner, 10 ms);
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  clk <= not clk after clk_period / 2;
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  ------------------------------------------------------------------------------
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  main : process
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    variable rnd : RandomPType;
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    variable data, got : std_logic_vector(data_width - 1 downto 0);
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    constant num_words : integer := 1000;
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    constant bytes_per_word : integer := data_width / 8;
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    variable address : integer;
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    variable buf : buffer_t;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    buf := allocate(memory, num_words * bytes_per_word);
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    if run("read_write_data") then
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      for i in 0 to num_words - 1 loop
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        address := i * bytes_per_word;
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        data := rnd.RandSLV(data'length);
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        set_expected_word(memory, address, data);
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        write_bus(net, axi_master, address, data);
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        read_bus(net, axi_master, address, got);
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        check_equal(got, data, line_num => 87, file_name => "tb_axi_to_axi_lite.vhd");
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      end loop;
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    end if;
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    check_expected_was_written(memory);
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  axi_master_inst : entity bfm.axi_master
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    generic map (
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      bus_handle => axi_master
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    )
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    port map (
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      clk => clk,
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      axi_read_m2s => axi_m2s.read,
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      axi_read_s2m => axi_s2m.read,
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      axi_write_m2s => axi_m2s.write,
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      axi_write_s2m => axi_s2m.write
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    );
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  ------------------------------------------------------------------------------
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  axi_lite_slave_inst : entity bfm.axi_lite_slave
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    generic map (
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      axi_read_slave => axi_read_slave,
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      axi_write_slave => axi_write_slave,
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      data_width => data_width
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    )
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    port map (
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      clk => clk,
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      --
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      axi_lite_read_m2s => axi_lite_m2s.read,
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      axi_lite_read_s2m => axi_lite_s2m.read,
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      --
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      axi_lite_write_m2s => axi_lite_m2s.write,
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      axi_lite_write_s2m => axi_lite_s2m.write
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    );
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  ------------------------------------------------------------------------------
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  dut : entity work.axi_to_axi_lite
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    generic map (
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      data_width => data_width
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    )
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    port map (
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      clk => clk,
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      axi_m2s => axi_m2s,
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      axi_s2m => axi_s2m,
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      axi_lite_m2s => axi_lite_m2s,
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      axi_lite_s2m => axi_lite_s2m
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    );
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end architecture;