GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_to_axi_lite_bus_error.vhd Lines: 47 47 100.0 %
Date: 2021-06-12 04:12:08 Branches: 256 335 76.4 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.bus_master_pkg.all;
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use vunit_lib.memory_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.com_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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library math;
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use math.math_pkg.all;
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use work.axi_lite_pkg.all;
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use work.axi_pkg.all;
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use work.axi_pkg.axi_resp_okay;
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use work.axi_pkg.axi_resp_slverr;
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entity tb_axi_to_axi_lite_bus_error is
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  generic (
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    data_width : integer;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_to_axi_lite_bus_error is
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  signal clk : std_logic := '0';
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  signal axi_m2s : axi_m2s_t;
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  signal axi_s2m : axi_s2m_t;
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  signal axi_lite_m2s : axi_lite_m2s_t;
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  signal axi_lite_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
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  constant correct_size : integer := log2(data_width / 8);
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  constant correct_len : integer := 0;
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begin
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  test_runner_watchdog(runner, 10 ms);
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  clk <= not clk after 2 ns;
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  ------------------------------------------------------------------------------
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  main : process
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    procedure test_ar(len, size : integer; resp : std_logic_vector) is
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    begin
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      axi_lite_s2m.read.ar.ready <= '1';
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      axi_m2s.read.ar.valid <= '1';
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      axi_m2s.read.ar.len <= to_unsigned(len, axi_m2s.read.ar.len'length);
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      axi_m2s.read.ar.size <= to_unsigned(size, axi_m2s.read.ar.size'length);
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      wait until (axi_m2s.read.ar.valid and axi_s2m.read.ar.ready) = '1' and rising_edge(clk);
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      axi_m2s.read.r.ready <= '1';
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      axi_lite_s2m.read.r.valid <= '1';
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      wait until (axi_s2m.read.r.valid and axi_m2s.read.r.ready) = '1' and rising_edge(clk);
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      check_equal(axi_s2m.read.r.resp, resp, line_num => 71, file_name => "tb_axi_to_axi_lite_bus_error.vhd");
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    end procedure;
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    procedure test_aw(len, size : integer; resp : std_logic_vector) is
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    begin
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      axi_lite_s2m.write.aw.ready <= '1';
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      axi_m2s.write.aw.valid <= '1';
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      axi_m2s.write.aw.len <= to_unsigned(len, axi_m2s.write.aw.len'length);
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      axi_m2s.write.aw.size <= to_unsigned(size, axi_m2s.write.aw.size'length);
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      wait until (axi_m2s.write.aw.valid and axi_s2m.write.aw.ready) = '1' and rising_edge(clk);
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      axi_m2s.write.b.ready <= '1';
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      axi_lite_s2m.write.b.valid <= '1';
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      wait until (axi_s2m.write.b.valid and axi_m2s.write.b.ready) = '1' and rising_edge(clk);
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      check_equal(axi_s2m.write.b.resp, resp, line_num => 87, file_name => "tb_axi_to_axi_lite_bus_error.vhd");
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    -- All should be okay before test
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    test_ar(correct_len, correct_size, axi_resp_okay);
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    test_aw(correct_len, correct_size, axi_resp_okay);
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    if run("ar_len_error") then
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      test_ar(correct_len + 1, correct_size, axi_resp_slverr);
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    elsif run("ar_size_error") then
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      test_ar(correct_len, correct_size + 1, axi_resp_slverr);
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    elsif run("aw_len_error") then
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      test_aw(correct_len + 1, correct_size, axi_resp_slverr);
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    elsif run("aw_size_error") then
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      test_aw(correct_len, correct_size + 1, axi_resp_slverr);
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    end if;
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    -- The upcoming transaction after an offending transaction should be all okay
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    test_ar(correct_len, correct_size, axi_resp_okay);
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    test_aw(correct_len, correct_size, axi_resp_okay);
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.axi_to_axi_lite
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    generic map (
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      data_width => data_width
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    )
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    port map (
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      clk => clk,
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      axi_m2s => axi_m2s,
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      axi_s2m => axi_s2m,
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      axi_lite_m2s => axi_lite_m2s,
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      axi_lite_s2m => axi_lite_s2m
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    );
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end architecture;