GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/axi/tb_axi_to_axi_lite_vec.vhd Lines: 49 49 100.0 %
Date: 2021-06-12 04:12:08 Branches: 254 333 76.3 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.com_context;
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context vunit_lib.vc_context;
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library common;
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use common.addr_pkg.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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use reg_file.reg_operations_pkg.all;
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library axi;
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use axi.axi_pkg.all;
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use axi.axi_lite_pkg.all;
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library bfm;
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entity tb_axi_to_axi_lite_vec is
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  generic (
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    pipeline : boolean;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_axi_to_axi_lite_vec is
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  constant axi_lite_slaves : addr_and_mask_vec_t(0 to 6 - 1) := (
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    0 => (addr => x"0000_0000", mask => x"0000_7000"),
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    1 => (addr => x"0000_1000", mask => x"0000_7000"),
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    2 => (addr => x"0000_2000", mask => x"0000_7000"),
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    3 => (addr => x"0000_3000", mask => x"0000_7000"),
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    4 => (addr => x"0000_4000", mask => x"0000_7000"),
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    5 => (addr => x"0000_5000", mask => x"0000_7000")
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  );
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  constant reg_map : reg_definition_vec_t(0 to 2 - 1) := (
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    (idx => 0, reg_type => r_w),
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    (idx => 1, reg_type => r_w)
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  );
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  constant clk_axi_period : time := 7 ns;
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  constant clk_axi_lite_slow_period : time := 3 ns;
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  constant clk_axi_lite_fast_period : time := 11 ns;
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  -- Two of the slaves have same clock as axi clock. Two have a faster clock
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  -- and two have a slower. Corresponds to the clock assignments further below.
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  constant clocks_are_the_same : boolean_vector(axi_lite_slaves'range) :=
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    (0 => true, 1 => true, 2 => false, 3 => false, 4 => false, 5 => false);
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  signal clk_axi : std_logic := '0';
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  signal clk_axi_lite_vec : std_logic_vector(axi_lite_slaves'range) := (others => '0');
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  signal axi_m2s : axi_m2s_t;
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  signal axi_s2m : axi_s2m_t;
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  signal axi_lite_m2s_vec : axi_lite_m2s_vec_t(axi_lite_slaves'range);
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  signal axi_lite_s2m_vec : axi_lite_s2m_vec_t(axi_lite_slaves'range);
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begin
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  clk_axi <= not clk_axi after clk_axi_period / 2;
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  clk_axi_lite_vec(0) <= not clk_axi_lite_vec(0) after clk_axi_period / 2;
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  clk_axi_lite_vec(1) <= not clk_axi_lite_vec(1) after clk_axi_period / 2;
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  clk_axi_lite_vec(2) <= not clk_axi_lite_vec(2) after clk_axi_lite_slow_period / 2;
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  clk_axi_lite_vec(3) <= not clk_axi_lite_vec(3) after clk_axi_lite_slow_period / 2;
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  clk_axi_lite_vec(4) <= not clk_axi_lite_vec(4) after clk_axi_lite_fast_period / 2;
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  clk_axi_lite_vec(5) <= not clk_axi_lite_vec(5) after clk_axi_lite_fast_period / 2;
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  test_runner_watchdog(runner, 2 ms);
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  ------------------------------------------------------------------------------
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  main : process
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    constant beef : std_logic_vector(32 - 1 downto 0) := x"beef_beef";
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    constant dead : std_logic_vector(32 - 1 downto 0) := x"dead_dead";
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  begin
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    test_runner_setup(runner, runner_cfg);
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    for slave_under_test_idx in axi_lite_slaves'range loop
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      for slave_idx in axi_lite_slaves'range loop
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        -- Write init value to all
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        write_reg(net, 0, beef, axi_lite_slaves(slave_idx).addr);
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        check_reg_equal(net, 0, beef, axi_lite_slaves(slave_idx).addr);
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      end loop;
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      -- Write special value to one of them
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      write_reg(net, 0, dead, axi_lite_slaves(slave_under_test_idx).addr);
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      for slave_idx in axi_lite_slaves'range loop
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        if slave_idx = slave_under_test_idx then
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          -- Check special value
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          check_reg_equal(net, 0, dead, axi_lite_slaves(slave_idx).addr);
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        else
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          -- The others should still have old value
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          check_reg_equal(net, 0, beef, axi_lite_slaves(slave_idx).addr);
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        end if;
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      end loop;
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    end loop;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  axi_master_inst : entity bfm.axi_master
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    generic map (
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      bus_handle => regs_bus_master
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    )
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    port map (
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      clk => clk_axi,
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      axi_read_m2s => axi_m2s.read,
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      axi_read_s2m => axi_s2m.read,
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      axi_write_m2s => axi_m2s.write,
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      axi_write_s2m => axi_s2m.write
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    );
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  ------------------------------------------------------------------------------
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  register_maps : for slave in axi_lite_slaves'range generate
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    axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
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    generic map (
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      regs => reg_map
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    )
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    port map (
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      clk => clk_axi_lite_vec(slave),
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      axi_lite_m2s => axi_lite_m2s_vec(slave),
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      axi_lite_s2m => axi_lite_s2m_vec(slave)
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    );
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  end generate;
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  ------------------------------------------------------------------------------
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  dut : entity work.axi_to_axi_lite_vec
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  generic map (
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    axi_lite_slaves => axi_lite_slaves,
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    clocks_are_the_same => clocks_are_the_same,
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    pipeline => pipeline,
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    data_width => reg_width
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  )
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  port map (
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    clk_axi => clk_axi,
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    axi_m2s => axi_m2s,
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    axi_s2m => axi_s2m,
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    clk_axi_lite_vec => clk_axi_lite_vec,
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    axi_lite_m2s_vec => axi_lite_m2s_vec,
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    axi_lite_s2m_vec => axi_lite_s2m_vec
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  );
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end architecture;