GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/bfm/axi_lite_write_slave.vhd Lines: 22 22 100.0 %
Date: 2021-06-12 04:12:08 Branches: 40 68 58.8 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library axi;
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use axi.axi_pkg.all;
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use axi.axi_lite_pkg.all;
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library vunit_lib;
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context vunit_lib.vc_context;
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entity axi_lite_write_slave is
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  generic (
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    axi_slave : axi_slave_t;
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    data_width : integer
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  );
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  port (
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    clk : in std_logic;
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    --
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    axi_lite_write_m2s : in axi_lite_write_m2s_t := axi_lite_write_m2s_init;
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    axi_lite_write_s2m : out axi_lite_write_s2m_t := axi_lite_write_s2m_init
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  );
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end entity;
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architecture a of axi_lite_write_slave is
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  constant len : std_logic_vector(axi_a_len_sz - 1 downto 0) := std_logic_vector(to_len(1));
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  constant size : std_logic_vector(axi_a_size_sz - 1 downto 0) :=
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    std_logic_vector(to_size(data_width));
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  -- Using "open" not ok in GHDL: unconstrained port "rid" must be connected
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  signal bid, aid : std_logic_vector(8 - 1 downto 0) := (others => '0');
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  signal awaddr : std_logic_vector(axi_lite_write_m2s.aw.addr'range);
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begin
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  ------------------------------------------------------------------------------
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  axi_write_slave_inst : entity vunit_lib.axi_write_slave
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    generic map (
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      axi_slave => axi_slave
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    )
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    port map (
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      aclk => clk,
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      --
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      awvalid => axi_lite_write_m2s.aw.valid,
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      awready => axi_lite_write_s2m.aw.ready,
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      awid => aid,
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      awaddr => awaddr,
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      awlen => len,
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      awsize => size,
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      awburst => axi_a_burst_fixed,
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      --
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      wvalid => axi_lite_write_m2s.w.valid,
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      wready => axi_lite_write_s2m.w.ready,
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      wdata => axi_lite_write_m2s.w.data(data_width - 1 downto 0),
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      wstrb => axi_lite_write_m2s.w.strb,
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      wlast => '1',
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      --
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      bvalid => axi_lite_write_s2m.b.valid,
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      bready => axi_lite_write_m2s.b.ready,
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      bid => bid,
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      bresp => axi_lite_write_s2m.b.resp
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    );
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  awaddr <= std_logic_vector(axi_lite_write_m2s.aw.addr);
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end architecture;