GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/bfm/axi_master.vhd Lines: 33 33 100.0 %
Date: 2021-06-12 04:12:08 Branches: 187 275 68.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library math;
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use math.math_pkg.all;
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library axi;
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use axi.axi_pkg.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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entity axi_master is
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  generic (
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    bus_handle : bus_master_t
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  );
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  port (
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    clk : in std_logic;
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5119
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    axi_read_m2s : out axi_read_m2s_t := axi_read_m2s_init;
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    axi_read_s2m : in axi_read_s2m_t := axi_read_s2m_init;
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    axi_write_m2s : out axi_write_m2s_t := axi_write_m2s_init;
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    axi_write_s2m : in axi_write_s2m_t := axi_write_s2m_init
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  );
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end entity;
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architecture a of axi_master is
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  constant data_width : positive := data_length(bus_handle);
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  constant len : unsigned(axi_write_m2s.aw.len'range) := to_len(1);
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  constant size : unsigned(axi_write_m2s.aw.size'range) := to_size(data_width);
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  signal araddr, awaddr : std_logic_vector(address_length(bus_handle) - 1 downto 0);
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  signal rdata, wdata : std_logic_vector(data_width - 1 downto 0);
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  signal wstrb : std_logic_vector(byte_enable_length(bus_handle) - 1 downto 0);
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begin
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  ------------------------------------------------------------------------------
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  axi_read_m2s.ar.addr(araddr'range) <= unsigned(araddr);
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  axi_read_m2s.ar.len <= len;
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  axi_read_m2s.ar.size <= size;
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  axi_read_m2s.ar.burst <= axi_a_burst_incr;
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  rdata <= axi_read_s2m.r.data(rdata'range);
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  axi_write_m2s.aw.addr(awaddr'range) <= unsigned(awaddr);
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  axi_write_m2s.aw.len <= len;
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  axi_write_m2s.aw.size <= size;
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  axi_write_m2s.aw.burst <= axi_a_burst_incr;
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  axi_write_m2s.w.data(wdata'range) <= wdata;
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  axi_write_m2s.w.last <= '1';
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  axi_write_m2s.w.strb(wstrb'range) <= wstrb;
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  ------------------------------------------------------------------------------
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  axi_lite_master_inst : entity vunit_lib.axi_lite_master
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  generic map (
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    bus_handle => bus_handle
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  )
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  port map (
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    aclk => clk,
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    arready => axi_read_s2m.ar.ready,
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    arvalid => axi_read_m2s.ar.valid,
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    araddr => araddr,
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    rready => axi_read_m2s.r.ready,
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    rvalid => axi_read_s2m.r.valid,
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    rdata => rdata,
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    rresp => axi_read_s2m.r.resp,
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    awready => axi_write_s2m.aw.ready,
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    awvalid => axi_write_m2s.aw.valid,
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    awaddr => awaddr,
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    wready => axi_write_s2m.w.ready,
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    wvalid => axi_write_m2s.w.valid,
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    wdata => wdata,
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    wstrb => wstrb,
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    bready => axi_write_m2s.b.ready,
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    bvalid => axi_write_s2m.b.valid,
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    bresp => axi_write_s2m.b.resp
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  );
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end architecture;