GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/bfm/axi_read_slave.vhd Lines: 0 23 0.0 %
Date: 2021-06-12 04:12:08 Branches: 0 124 0.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vc_context;
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library axi;
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use axi.axi_pkg.all;
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entity axi_read_slave is
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  generic (
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    axi_slave : axi_slave_t;
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    data_width : positive;
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    -- Note that the VUnit BFM creates and integer_vector_ptr of length 2**id_width, so a large
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    -- value for id_width might crash your simulator.
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    id_width : natural := 8
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  );
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  port (
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    clk : in std_logic;
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    axi_read_m2s : in axi_read_m2s_t := axi_read_m2s_init;
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    axi_read_s2m : out axi_read_s2m_t := axi_read_s2m_init
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  );
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end entity;
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architecture a of axi_read_slave is
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  signal arid, rid : std_logic_vector(id_width - 1 downto 0);
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  signal araddr : std_logic_vector(axi_read_m2s.ar.addr'range );
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  signal arlen : std_logic_vector(axi_read_m2s.ar.len'range );
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  signal arsize : std_logic_vector(axi_read_m2s.ar.size'range );
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begin
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  ------------------------------------------------------------------------------
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  axi_read_slave_inst : entity vunit_lib.axi_read_slave
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    generic map (
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      axi_slave => axi_slave
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    )
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    port map (
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      aclk => clk,
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      arvalid => axi_read_m2s.ar.valid,
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      arready => axi_read_s2m.ar.ready,
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      arid => arid,
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      araddr => araddr,
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      arlen => arlen,
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      arsize => arsize,
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      arburst => axi_read_m2s.ar.burst,
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      rvalid => axi_read_s2m.r.valid,
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      rready => axi_read_m2s.r.ready,
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      rid => rid,
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      rdata => axi_read_s2m.r.data(data_width - 1 downto 0),
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      rresp => axi_read_s2m.r.resp,
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      rlast => axi_read_s2m.r.last
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    );
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  arid <= std_logic_vector(axi_read_m2s.ar.id(id_width - 1 downto 0));
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  araddr <= std_logic_vector(axi_read_m2s.ar.addr);
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  arlen <= std_logic_vector(axi_read_m2s.ar.len);
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  arsize <= std_logic_vector(axi_read_m2s.ar.size);
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  axi_read_s2m.r.id(id_width - 1 downto 0) <= unsigned(rid);
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end architecture;