GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/bfm/axi_slave.vhd Lines: 9 9 100.0 %
Date: 2021-06-12 04:12:08 Branches: 80 97 82.5 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
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-- Will instantiate read and/or write BFMs based on what generics are provided.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vc_context;
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library axi;
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use axi.axi_pkg.all;
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use work.axi_slave_pkg.all;
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entity axi_slave is
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  generic (
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    axi_read_slave : axi_slave_t := axi_slave_init;
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    axi_write_slave : axi_slave_t := axi_slave_init;
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    data_width : positive;
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    -- Note that the VUnit BFM creates and integer_vector_ptr of length 2**id_width, so a large
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    -- value for id_width might crash your simulator.
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    id_width : natural := 8;
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    w_fifo_depth : natural := 0
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  );
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  port (
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    clk : in std_logic;
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    --
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    axi_read_m2s : in axi_read_m2s_t := axi_read_m2s_init;
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    axi_read_s2m : out axi_read_s2m_t := axi_read_s2m_init;
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    --
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    axi_write_m2s : in axi_write_m2s_t := axi_write_m2s_init;
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    axi_write_s2m : out axi_write_s2m_t := axi_write_s2m_init
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  );
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end entity;
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architecture a of axi_slave is
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begin
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  ------------------------------------------------------------------------------
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  axi_read_slave_gen : if axi_read_slave /= axi_slave_init generate
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    axi_read_slave_inst : entity work.axi_read_slave
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      generic map (
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        axi_slave => axi_read_slave,
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        data_width => data_width,
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        id_width => id_width
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      )
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      port map (
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        clk => clk,
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        axi_read_m2s => axi_read_m2s,
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        axi_read_s2m => axi_read_s2m
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      );
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  end generate;
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  ------------------------------------------------------------------------------
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  axi_write_slave_gen : if axi_write_slave /= axi_slave_init generate
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    axi_write_slave_inst : entity work.axi_write_slave
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      generic map (
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        axi_slave => axi_write_slave,
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        data_width => data_width,
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        id_width => id_width,
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        w_fifo_depth => w_fifo_depth
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      )
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      port map (
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        clk => clk,
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        axi_write_m2s => axi_write_m2s,
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        axi_write_s2m => axi_write_s2m
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      );
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  end generate;
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end architecture;