GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/common/debounce.vhd Lines: 15 15 100.0 %
Date: 2021-06-12 04:12:08 Branches: 23 36 63.9 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Simple debounce mechanism to be used with e.g. the signal from a button or
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-- dip switch. It eliminates noise by requiring the input to have a stable
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-- value for a specified number of clock cycles before propagating the value.
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--
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-- Uses a resync_level block (async_reg chain) to make sure the input is not
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-- metastable.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library resync;
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entity debounce is
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  generic (
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    -- Number of cycles the input must be stable for the value to propagate to the result side.
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    stable_count : positive
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  );
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  port (
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    -- Input value that may be metastable and noisy
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    noisy_input : in std_logic := '0';
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    --
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    clk : in std_logic;
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    stable_result : out std_logic := '0'
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  );
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end entity;
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architecture a of debounce is
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  signal noisy_input_resync : std_logic := '0';
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  signal num_cycles_with_new_value : integer range 0 to stable_count - 1 := 0;
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begin
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  ------------------------------------------------------------------------------
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  resync_level_inst : entity resync.resync_level
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    generic map (
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      -- We do not know the input clock, so set this to false
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      enable_input_register => false
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    )
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    port map (
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      data_in => noisy_input,
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      --
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      clk_out => clk,
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      data_out => noisy_input_resync
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    );
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  ------------------------------------------------------------------------------
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  main : process
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  begin
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    wait until rising_edge(clk);
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    if noisy_input_resync = stable_result then
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      num_cycles_with_new_value <= 0;
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    else
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      if num_cycles_with_new_value = stable_count - 1 then
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        stable_result <= noisy_input_resync;
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        num_cycles_with_new_value <= 0;
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      else
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        num_cycles_with_new_value <= num_cycles_with_new_value + 1;
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      end if;
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    end if;
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  end process;
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end architecture;