GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/common/tb_clock_counter.vhd Lines: 25 25 100.0 %
Date: 2021-06-12 04:12:08 Branches: 67 108 62.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library math;
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use math.math_pkg.all;
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entity tb_clock_counter is
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  generic (
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    reference_clock_rate_mhz : positive;
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    target_clock_rate_mhz : positive;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_clock_counter is
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  constant resolution_bits : positive := 10;
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  constant max_relation_bits : positive := 8;
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  signal reference_clock, target_clock : std_logic := '0';
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  signal target_tick_count : unsigned(resolution_bits + max_relation_bits - 1 downto 0) :=
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    (others => '0');
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  constant reference_clock_period : time := (1.0 / real(reference_clock_rate_mhz)) * (1 us);
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  constant target_clock_period : time := (1.0 / real(target_clock_rate_mhz)) * (1 us);
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  constant expected_target_tick_count : real :=
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    2.0 ** resolution_bits * real(target_clock_rate_mhz) / real(reference_clock_rate_mhz);
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begin
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28690
  test_runner_watchdog(runner, 1 ms);
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28678
  reference_clock <= not reference_clock after reference_clock_period / 2;
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  target_clock <= not target_clock after target_clock_period / 2;
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  ------------------------------------------------------------------------------
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  main : process
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  begin
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    test_runner_setup(runner, runner_cfg);
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    if run("test_target_tick_count") then
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      -- For the first 2 ** resolution_bits cycles, the value is zero,
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      -- the next 2 ** resolution_bits cycles, the value is almost correct but a little too low.
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      for wait_cycle in 0 to 2 * 2 ** resolution_bits - 1 loop
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        wait until rising_edge(reference_clock);
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      end loop;
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      -- In all upcoming cycles however, the value shall be correct.
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      for check_iteration in 0 to 5 * 2 ** resolution_bits loop
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        wait until rising_edge(reference_clock);
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        check_equal(
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          real(to_integer(target_tick_count)),
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          expected_target_tick_count,
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          msg=>"check_iteration=" & to_string(check_iteration),
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          max_diff=>1.0
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        , line_num => 65, file_name => "tb_clock_counter.vhd");
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      end loop;
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.clock_counter
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    generic map (
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      resolution_bits => resolution_bits,
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      max_relation_bits => max_relation_bits
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    )
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    port map (
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      target_clock => target_clock,
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      --
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      reference_clock => reference_clock,
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      target_tick_count => target_tick_count
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    );
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end architecture;