GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/common/tb_handshake_splitter.vhd Lines: 65 65 100.0 %
Date: 2021-06-12 04:12:08 Branches: 208 323 64.4 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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use work.types_pkg.all;
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entity tb_handshake_splitter is
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  generic (
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_handshake_splitter is
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  signal clk : std_logic := '0';
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61181
  constant clk_period : time := 10 ns;
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  signal input_data : std_logic_vector(8 - 1 downto 0);
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  signal input_ready, input_valid : std_logic := '0';
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  signal output0_ready, output0_valid, output1_ready, output1_valid : std_logic := '0';
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  constant num_words : integer := 2_000;
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  constant axi_stream_master : axi_stream_master_t := new_axi_stream_master(
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    data_length => input_data'length,
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    protocol_checker => new_axi_stream_protocol_checker(
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      logger => get_logger("axi_stream_master"), data_length => input_data'length));
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  signal data_check0_done, data_check1_done : boolean := false;
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  shared variable rnd : RandomPType;
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  signal data_queue0 : queue_t := new_queue;
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  signal data_queue1 : queue_t := new_queue;
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begin
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  test_runner_watchdog(runner, 1 ms);
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25761
  clk <= not clk after clk_period / 2;
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  ------------------------------------------------------------------------------
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  main : process
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    variable data : std_logic_vector(input_data'range) := (others => '0');
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    variable last_dummy : std_logic := '1';
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    if run("test_data") then
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      for i in 1 to num_words loop
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        data := rnd.RandSlv(data'length);
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        push_axi_stream(net, axi_stream_master, tdata => data, tlast => last_dummy);
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        push(data_queue0, data);
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        push(data_queue1, data);
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      end loop;
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    end if;
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    wait until data_check0_done and data_check1_done;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  data_check0 : process
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    variable data : std_logic_vector(input_data'range) := (others => '0');
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  begin
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    for i in 1 to num_words loop
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      output0_ready <= '1';
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      wait until (output0_ready and output0_valid) = '1' and rising_edge(clk);
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      output0_ready <= '0';
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      data := pop(data_queue0);
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      check_equal(input_data, data, line_num => 89, file_name => "tb_handshake_splitter.vhd");
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      for jitter in 1 to rnd.RandInt(2) loop
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14100
        wait until rising_edge(clk);
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      end loop;
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    end loop;
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    assert is_empty(data_queue0);
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    data_check0_done <= true;
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    wait;
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  end process;
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  ------------------------------------------------------------------------------
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  output0_axi_stream_protocol_checker_inst : entity vunit_lib.axi_stream_protocol_checker
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    generic map (
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      protocol_checker => new_axi_stream_protocol_checker(
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        logger => get_logger("output0"), data_length => input_data'length)
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    )
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    port map (
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      aclk => clk,
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      tvalid => output0_valid,
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      tready => output0_ready,
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      tdata => input_data
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    );
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  ------------------------------------------------------------------------------
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  data_check1 : process
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    variable data : std_logic_vector(input_data'range) := (others => '0');
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  begin
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    for i in 1 to num_words loop
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      output1_ready <= '1';
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      wait until (output1_ready and output1_valid) = '1' and rising_edge(clk);
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      output1_ready <= '0';
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      data := pop(data_queue1);
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      check_equal(input_data, data, line_num => 126, file_name => "tb_handshake_splitter.vhd");
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      for jitter in 1 to rnd.RandInt(2) loop
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27760
        wait until rising_edge(clk);
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      end loop;
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    end loop;
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    assert is_empty(data_queue1);
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    data_check1_done <= true;
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    wait;
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  end process;
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  ------------------------------------------------------------------------------
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  output1_axi_stream_protocol_checker_inst : entity vunit_lib.axi_stream_protocol_checker
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    generic map (
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      protocol_checker => new_axi_stream_protocol_checker(
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        logger => get_logger("output1"), data_length => input_data'length)
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    )
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    port map (
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      aclk => clk,
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      tvalid => output1_valid,
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      tready => output1_ready,
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      tdata => input_data
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    );
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  ------------------------------------------------------------------------------
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  axi_stream_master_inst : entity vunit_lib.axi_stream_master
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  generic map(
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    master => axi_stream_master
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  )
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  port map(
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    aclk   => clk,
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    tvalid => input_valid,
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    tready => input_ready,
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    tdata  => input_data
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  );
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  ------------------------------------------------------------------------------
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  dut : entity work.handshake_splitter
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    port map (
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      clk => clk,
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      --
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      input_ready => input_ready,
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      input_valid => input_valid,
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      --
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      output0_ready => output0_ready,
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      output0_valid => output0_valid,
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      --
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      output1_ready => output1_ready,
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      output1_valid => output1_valid
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    );
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end architecture;