GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/common/tb_periodic_pulser.vhd Lines: 40 40 100.0 %
Date: 2021-06-12 04:12:08 Branches: 93 151 61.6 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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entity tb_periodic_pulser is
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  generic (
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    period : integer range 2 to integer'high;
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    shift_register_length : positive;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_periodic_pulser is
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  signal clk : std_logic := '0';
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  signal count_enable : std_logic := '1';
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  signal pulse : std_logic := '0';
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  signal target_clock : std_logic;
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  signal start_test, test_done : boolean := false;
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begin
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  clk <= not clk after 5 ns;
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  test_runner_watchdog(runner, 1 ms);
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  ------------------------------------------------------------------------------
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  main : process
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  begin
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    test_runner_setup(runner, runner_cfg);
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    wait until rising_edge(clk);
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    start_test <= true;
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    wait until rising_edge(clk) and test_done;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  stimuli : process
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    variable rnd : RandomPType;
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  begin
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    wait until rising_edge(clk) and start_test;
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    loop
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      wait until rising_edge(clk);
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      count_enable <= rnd.RandSlv(1)(1);
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    end loop;
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  end process;
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  ------------------------------------------------------------------------------
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  check : process
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    constant num_pulses_to_check : integer := 3;
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    variable tick_count : integer range 0 to period - 1;
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    variable num_pulses : integer range 0 to num_pulses_to_check := 0;
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    variable expected_pulse : std_logic := '0';
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  begin
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    wait until rising_edge(clk);
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    expected_pulse := '0';
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    if count_enable then
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      if tick_count = period - 1 then
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        tick_count := 0;
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        expected_pulse := '1';
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      else
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        tick_count := tick_count + 1;
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      end if;
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    end if;
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    check_equal(pulse, expected_pulse, "Pulse seen at unexpected time", line_num => 88, file_name => "tb_periodic_pulser.vhd");
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    if expected_pulse then
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      num_pulses := num_pulses + 1;
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      if num_pulses = num_pulses_to_check then
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        test_done <= true;
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      end if;
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    end if;
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.periodic_pulser
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    generic map (
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      period => period,
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      shift_register_length => shift_register_length)
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    port map (
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      clk => clk,
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      count_enable => count_enable,
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      pulse => pulse
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      );
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end architecture;