GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/ddr_buffer/ddr_buffer_sim_pkg.vhd Lines: 14 14 100.0 %
Date: 2021-06-12 04:12:08 Branches: 90 153 58.8 %

Line Branch Exec Source
1




























132
-- -------------------------------------------------------------------------------------------------
2
-- Copyright (c) Lukas Vik. All rights reserved.
3
--
4
-- This file is part of the tsfpga project.
5
-- https://tsfpga.com
6
-- https://gitlab.com/tsfpga/tsfpga
7
-- -------------------------------------------------------------------------------------------------
8
9
library ieee;
10
use ieee.std_logic_1164.all;
11
12
library vunit_lib;
13
use vunit_lib.random_pkg.all;
14
context vunit_lib.vunit_context;
15
context vunit_lib.vc_context;
16
17
library osvvm;
18
use osvvm.RandomPkg.all;
19
20
library common;
21
use common.addr_pkg.all;
22
23
library reg_file;
24
use reg_file.reg_operations_pkg.all;
25
26
use work.ddr_buffer_regs_pkg.all;
27
use work.example_reg_operations_pkg.all;
28
29
30
package ddr_buffer_sim_pkg is
31
32
  procedure run_ddr_buffer_test(signal net : inout network_t;
33
                                memory : in memory_t;
34
                                rnd : inout RandomPType;
35
                                regs_base_address : in addr_t := (others => '0'));
36
37
end package;
38
39
package body ddr_buffer_sim_pkg is
40
41




240
  procedure run_ddr_buffer_test(signal net : inout network_t;
42
                                memory : in memory_t;
43
                                rnd : inout RandomPType;
44
                                regs_base_address : in addr_t := (others => '0')) is
45
6
    constant burst_length_bytes : integer :=
46
      ddr_buffer_constant_burst_length_beats * (ddr_buffer_constant_axi_data_width / 8);
47
6
    variable memory_data : integer_array_t := null_integer_array;
48
6
    variable buf : buffer_t;
49
  begin
50
6
    for current_addr_index in 0 to ddr_buffer_addrs_array_length - 1 loop
51
24
      random_integer_array(rnd, memory_data, width=>burst_length_bytes, bits_per_word=>8);
52
53
12
      buf := write_integer_array(memory, memory_data, "read data", permissions=>read_only);
54

26
      write_reg(net, ddr_buffer_addrs_read_addr(current_addr_index), base_address(buf), regs_base_address);
55
56
12
      buf := set_expected_integer_array(memory, memory_data, "write data", permissions=>write_only);
57

48
      write_reg(net, ddr_buffer_addrs_write_addr(current_addr_index), base_address(buf), regs_base_address);
58
    end loop;
59
60
12
    write_command(net, ddr_buffer_command_start, regs_base_address);
61
100
    wait_for_status_bit(net, ddr_buffer_status_idle, regs_base_address);
62
63

168
    check_expected_was_written(memory);
64
  end procedure;
65
66
end package body;