GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/ddr_buffer/ddr_buffer_top.vhd Lines: 56 56 100.0 %
Date: 2021-06-12 04:12:08 Branches: 219 293 74.7 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library axi;
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use axi.axi_pkg.all;
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use axi.axi_lite_pkg.all;
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library reg_file;
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use work.ddr_buffer_regs_pkg.all;
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entity ddr_buffer_top is
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  port (
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    clk : in std_logic;
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    axi_read_m2s : out axi_read_m2s_t := axi_read_m2s_init;
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    axi_read_s2m : in axi_read_s2m_t;
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    axi_write_m2s : out axi_write_m2s_t := axi_write_m2s_init;
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    axi_write_s2m : in axi_write_s2m_t;
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    regs_m2s : in axi_lite_m2s_t;
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    regs_s2m : out axi_lite_s2m_t := axi_lite_s2m_init
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  );
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end entity;
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architecture a of ddr_buffer_top is
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  type ctrl_state_t is (idle, start, wait_for_address_transactions, running);
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  signal ctrl_state : ctrl_state_t := idle;
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  signal current_addr_index : integer range 0 to ddr_buffer_addrs_array_length - 1 := 0;
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  signal regs_up, regs_down : ddr_buffer_regs_t := ddr_buffer_regs_init;
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  signal counter : unsigned(ddr_buffer_status_counter) := (others => '0');
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begin
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  regs_up(ddr_buffer_status)(ddr_buffer_status_counter) <= std_logic_vector(counter);
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  ------------------------------------------------------------------------------
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  axi_read_m2s.ar.addr(regs_down(0)'range) <= unsigned(regs_down(ddr_buffer_addrs_read_addr(current_addr_index)));
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  axi_read_m2s.ar.len <= to_len(ddr_buffer_constant_burst_length_beats);
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  axi_read_m2s.ar.size <= to_size(ddr_buffer_constant_axi_data_width);
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  axi_read_m2s.ar.burst <= axi_a_burst_incr;
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  ------------------------------------------------------------------------------
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  axi_write_m2s.aw.addr(regs_down(0)'range) <= unsigned(regs_down(ddr_buffer_addrs_write_addr(current_addr_index)));
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  axi_write_m2s.aw.len <= to_len(ddr_buffer_constant_burst_length_beats);
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  axi_write_m2s.aw.size <= to_size(ddr_buffer_constant_axi_data_width);
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  axi_write_m2s.aw.burst <= axi_a_burst_incr;
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  axi_write_m2s.w.strb <= to_strb(ddr_buffer_constant_axi_data_width);
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  axi_write_m2s.b.ready <= '1';
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  ------------------------------------------------------------------------------
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  axi_read_m2s.r.ready <= axi_write_s2m.w.ready;
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  axi_write_m2s.w.valid <= axi_read_s2m.r.valid and axi_read_m2s.r.ready;
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  axi_write_m2s.w.data <= axi_read_s2m.r.data;
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  axi_write_m2s.w.last <= axi_read_s2m.r.last;
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  ------------------------------------------------------------------------------
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  ctrl : process
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    variable ar_done, aw_done : boolean := false;
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  begin
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    wait until rising_edge(clk);
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    case ctrl_state is
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      when idle =>
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        regs_up(ddr_buffer_status)(ddr_buffer_status_idle) <= '1';
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        ar_done := false;
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        aw_done := false;
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        if regs_down(ddr_buffer_command)(ddr_buffer_command_start) then
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          ctrl_state <= start;
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          regs_up(ddr_buffer_status)(ddr_buffer_status_idle) <= '0';
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        end if;
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      when start =>
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        axi_read_m2s.ar.valid <= '1';
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        axi_write_m2s.aw.valid <= '1';
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        ctrl_state <= wait_for_address_transactions;
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      when wait_for_address_transactions =>
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        if axi_read_m2s.ar.valid and axi_read_s2m.ar.ready then
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          axi_read_m2s.ar.valid <= '0';
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          ar_done := true;
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        end if;
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        if axi_write_m2s.aw.valid and axi_write_s2m.aw.ready then
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          axi_write_m2s.aw.valid <= '0';
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          aw_done := true;
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        end if;
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        if ar_done and aw_done then
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          ctrl_state <= running;
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        end if;
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      when running =>
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        if axi_write_m2s.w.valid and axi_write_s2m.w.ready and axi_write_m2s.w.last then
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          counter <= counter + 1;
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          if current_addr_index = ddr_buffer_addrs_array_length - 1 then
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            current_addr_index <= 0;
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            ctrl_state <= idle;
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          else
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            current_addr_index <= current_addr_index + 1;
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            ctrl_state <= start;
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          end if;
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        end if;
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    end case;
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  end process;
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  ------------------------------------------------------------------------------
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  axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
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    generic map (
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      regs => ddr_buffer_reg_map,
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      default_values => ddr_buffer_regs_init
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    )
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    port map (
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      clk => clk,
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      axi_lite_m2s => regs_m2s,
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      axi_lite_s2m => regs_s2m,
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      regs_up => regs_up,
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      regs_down => regs_down
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    );
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end architecture;