GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/ddr_buffer/example_reg_operations_pkg.vhd Lines: 19 19 100.0 %
Date: 2021-06-12 04:12:08 Branches: 87 155 56.1 %

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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library common;
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use common.addr_pkg.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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use reg_file.reg_operations_pkg.all;
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package example_reg_operations_pkg is
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  -- These convenience functions for the example modules rely on using the standard
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  -- register locations, definded below as well as in tsfpga_example_env.py.
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  constant config_reg : integer := 0;
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  constant command_reg : integer := 1;
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  constant status_reg : integer := 2;
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  constant irq_status_reg : integer := 3;
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  constant irq_mask_reg : integer := 4;
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  procedure write_command(
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    signal net : inout network_t;
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    bit : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure wait_for_any_status_bit(
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    signal net : inout network_t;
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    bits : in integer_vector;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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  procedure wait_for_status_bit(
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    signal net : inout network_t;
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    bit : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master);
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end;
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package body example_reg_operations_pkg is
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  procedure write_command(
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    signal net : inout network_t;
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    bit : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable register_value : reg_t := (others => '0');
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  begin
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    register_value(bit) := '1';
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    write_reg(net, command_reg, register_value, base_address, bus_handle);
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  end procedure;
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  procedure wait_for_any_status_bit(
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    signal net : inout network_t;
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    bits : in integer_vector;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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    variable read_value : reg_t;
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  begin
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    -- Returns when any of the specified bits are asserted
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    read_loop : while true loop
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      read_reg(net, status_reg, read_value, base_address, bus_handle);
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      for bits_vector_loop_index in bits'range loop
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        if read_value(bits(bits_vector_loop_index)) = '1' then
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          exit read_loop;
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        end if;
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      end loop;
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    end loop;
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  end procedure;
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  procedure wait_for_status_bit(
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    signal net : inout network_t;
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    bit : in integer;
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    base_address : in addr_t := (others => '0');
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    bus_handle : in bus_master_t := regs_bus_master) is
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  begin
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    wait_for_any_status_bit(net, (0 => bit), base_address, bus_handle);
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  end procedure;
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end;