GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/ddr_buffer/tb_ddr_buffer.vhd Lines: 46 46 100.0 %
Date: 2021-06-12 04:12:08 Branches: 184 250 73.6 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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library axi;
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use axi.axi_pkg.all;
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use axi.axi_lite_pkg.all;
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library bfm;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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use reg_file.reg_operations_pkg.all;
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use work.ddr_buffer_regs_pkg.all;
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use work.ddr_buffer_sim_pkg.all;
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entity tb_ddr_buffer is
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  generic (
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_ddr_buffer is
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540
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  signal clk : std_logic := '0';
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  signal axi_read_m2s : axi_read_m2s_t := axi_read_m2s_init;
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  signal axi_read_s2m : axi_read_s2m_t := axi_read_s2m_init;
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  signal axi_write_m2s : axi_write_m2s_t := axi_write_m2s_init;
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  signal axi_write_s2m : axi_write_s2m_t := axi_write_s2m_init;
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  signal regs_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
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  signal regs_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
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  constant axi_width : integer := 64;
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  constant burst_length : integer := 16;
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  constant burst_size_bytes : integer := burst_length * axi_width / 8;
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  constant memory : memory_t := new_memory;
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  constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
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    address_fifo_depth => 1,
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    memory => memory
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  );
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begin
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  test_runner_watchdog(runner, 1 ms);
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  clk <= not clk after 10 ns;
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  ------------------------------------------------------------------------------
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  main : process
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    variable rnd : RandomPType;
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    procedure check_counter(expected : natural) is
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      variable reg_value : reg_t := (others => '0');
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    begin
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      read_reg(net, ddr_buffer_status, reg_value);
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      check_equal(
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        unsigned(reg_value(ddr_buffer_status_counter)),
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        expected
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      , line_num => 76, file_name => "tb_ddr_buffer.vhd");
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    rnd.InitSeed(rnd'instance_name);
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    if run("test_ddr_buffer") then
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      check_counter(0);
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      run_ddr_buffer_test(net, memory, rnd);
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      check_counter(ddr_buffer_addrs_array_length);
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      run_ddr_buffer_test(net, memory, rnd);
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      check_counter(2 * ddr_buffer_addrs_array_length);
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    elsif run("test_version") then
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      check_reg_equal(net, ddr_buffer_version, ddr_buffer_constant_version);
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    end if;
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    check_expected_was_written(memory);
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  axi_lite_master_inst : entity bfm.axi_lite_master
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    generic map (
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      bus_handle => regs_bus_master
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    )
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    port map (
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      clk => clk,
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      axi_lite_m2s => regs_m2s,
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      axi_lite_s2m => regs_s2m
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    );
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  ------------------------------------------------------------------------------
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  axi_slave_inst : entity bfm.axi_slave
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    generic map (
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      axi_read_slave => axi_read_slave,
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      axi_write_slave => axi_write_slave,
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      data_width => axi_width
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    )
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    port map (
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      clk => clk,
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      axi_read_m2s => axi_read_m2s,
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      axi_read_s2m => axi_read_s2m,
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      axi_write_m2s => axi_write_m2s,
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      axi_write_s2m => axi_write_s2m
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    );
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  ------------------------------------------------------------------------------
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  dut : entity work.ddr_buffer_top
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    port map (
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      clk => clk,
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      axi_read_m2s => axi_read_m2s,
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      axi_read_s2m => axi_read_s2m,
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      axi_write_m2s => axi_write_m2s,
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      axi_write_s2m => axi_write_s2m,
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      regs_m2s => regs_m2s,
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      regs_s2m => regs_s2m
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    );
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end architecture;