GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/fifo/fifo.vhd Lines: 53 53 100.0 %
Date: 2021-06-12 04:12:08 Branches: 185 261 70.9 %

Line Branch Exec Source
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168
-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Synchronous FIFO.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library common;
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use common.attribute_pkg.all;
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use common.types_pkg.all;
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library math;
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use math.math_pkg.all;
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2464
entity fifo is
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  generic (
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    width : positive;
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    depth : positive;
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    -- Changing these levels from default value will increase logic footprint
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    almost_full_level : integer range 0 to depth := depth;
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    almost_empty_level : integer range 0 to depth := 0;
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    -- Set to true in order to use read_last and write_last
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    enable_last : boolean := false;
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    -- If enabled, read_valid will not be asserted until a full packet is available in
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    -- FIFO. I.e. when write_last has been received. Must set enable_last as well to use this.
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    enable_packet_mode : boolean := false;
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    -- Set to true in order to use the drop_packet port. Must set enable_packet_mode as
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    -- well to use this.
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    enable_drop_packet : boolean := false;
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    ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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    clk : in std_logic;
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    -- When packet_mode is enabled, this value will still reflect the number of words that are in
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    -- the FIFO RAM. This is not necessarily the same as the number of words that can be read, in
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    -- this mode.
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    level : out integer range 0 to depth := 0;
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    read_ready : in std_logic;
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    -- '1' if FIFO is not empty
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    read_valid : out std_logic := '0';
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    read_data : out std_logic_vector(width - 1 downto 0) := (others => '0');
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    -- Must set enable_last generic in order to use this
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    read_last : out std_logic := '0';
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    -- '1' if there are almost_empty_level or fewer words available to read
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    almost_empty : out std_logic := '1';
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    -- '1' if FIFO is not full
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    write_ready : out std_logic := '1';
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    write_valid : in std_logic;
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    write_data : in std_logic_vector(width - 1 downto 0);
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    -- Must set enable_last generic in order to use this
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    write_last : in std_logic := '-';
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    -- '1' if there are almost_full_level or more words available in the FIFO
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    almost_full : out std_logic := '0';
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    -- Drop the current packet (all words that have been writen since the previous write_last).
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    -- Must set enable_drop_packet generic in order to use this.
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    drop_packet : in std_logic := '0'
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  );
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end entity;
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architecture a of fifo is
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  -- Need one extra bit in the addresses to be able to make the distinction if the FIFO
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  -- is full or empty (where the addresses would otherwise be equal).
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  subtype fifo_addr_t is unsigned(num_bits_needed(2 * depth - 1) - 1 downto 0);
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712
  signal read_addr_next, read_addr : fifo_addr_t := (others => '0');
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1396
  signal write_addr_next, write_addr, write_addr_next_if_not_drop, write_addr_start_of_packet :
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    fifo_addr_t := (others => '0');
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  -- The part of the address that actually goes to the BRAM address port
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  subtype bram_addr_range is integer range num_bits_needed(depth - 1) - 1 downto 0;
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  signal num_lasts_in_fifo : integer range 0 to depth := 0;
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  signal should_drop_packet : std_logic := '0';
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begin
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  assert is_power_of_two(depth) report "Depth must be a power of two" severity failure;
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  assert enable_last or (not enable_packet_mode)
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    report "Must set enable_last for packet mode" severity failure;
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  assert enable_packet_mode or (not enable_drop_packet)
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    report "Must set enable_packet_mode for drop packet support" severity failure;
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  -- The flags will update one cycle after the write/read that puts them over/below the line.
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  -- Except for almost_empty when almost_empty_level is zero.
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  -- In that case, when a write puts it over the line there will be a two cycle latency, since
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  -- that write must propagate into the RAM before the data is valid to read.
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  -- For a read that puts it below the line there is always one cycle latency.
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  assign_almost_full : if almost_full_level = depth generate
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58
    almost_full <= not write_ready;
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  else generate
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26931
    almost_full <= to_sl(level > almost_full_level - 1);
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  end generate;
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  assign_almost_empty : if almost_empty_level = 0 generate
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28032
    almost_empty <= not read_valid;
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  else generate
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1500670
    almost_empty <= to_sl(level < almost_empty_level + 1);
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  end generate;
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  ------------------------------------------------------------------------------
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28
  status : process
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541
    variable num_lasts_in_fifo_next : integer range 0 to depth := 0;
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  begin
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1500610
    wait until rising_edge(clk);
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375152
    if enable_packet_mode then
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5485
      num_lasts_in_fifo_next := num_lasts_in_fifo
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        + to_int(write_ready and write_valid and write_last and not should_drop_packet)
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        - to_int(read_ready and read_valid and read_last);
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      -- We look at num_lasts_in_fifo_next since we need to update read_valid the same cycle when
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      -- the read happens.
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      -- We also look at num_lasts_in_fifo since a write needs an additional clock
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      -- cycle to propagate into the RAM. This is really only needed when the FIFO is empty and
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      -- a packet of length one is written. With this condition, there will be a two cycle latency
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      -- from write_last being written to read_valid being asserted.
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5485
      read_valid <= to_sl(num_lasts_in_fifo /= 0 and num_lasts_in_fifo_next /= 0);
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5485
      num_lasts_in_fifo <= num_lasts_in_fifo_next;
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    else
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369667
      read_valid <= to_sl(read_addr_next /= write_addr);
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    end if;
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    -- Note that write_ready looks at the write_addr_next that will be used if there is
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    -- no packet drop, even when drop_packet functionality is enabled. This is done to ease the
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    -- timing of write_ready which is often critical.
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    -- There is a functional difference only in the special case when the FIFO
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    -- goes full in the same cycle as drop_packet is sent. In that case, write_ready will be low
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    -- for one cycle and then go high the next.
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    --
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    -- Similarly write_ready looks at read_addr rather than read_addr_next, which eases the timing
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    -- of read_ready. There is a function difference when the FIFO is full and a read performed
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    -- makes the FIFO ready for another write. In this case, write_ready will be low
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    -- for one extra cycle after the read occurs, and then go high the next.
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375152
    write_ready <= to_sl(
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      read_addr(bram_addr_range) /= write_addr_next_if_not_drop(bram_addr_range)
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      or read_addr(read_addr'high) =  write_addr_next_if_not_drop(write_addr_next'high));
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375152
    if enable_drop_packet then
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1107
      if write_ready and write_valid and write_last and not should_drop_packet then
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375182
        write_addr_start_of_packet <= write_addr_next;
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      end if;
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    end if;
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    -- These signals however must have the updated values to be valid for the next cycle.
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2411611
    write_addr <= write_addr_next;
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2411611
    read_addr <= read_addr_next;
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    -- The level count shall always be correct, and hence uses the updated values. Note that this
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    -- can create some wonky situations, e.g. when level read as 1023 for a 1024 deep FIFO
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    -- but write_ready is false.
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    -- Also in packet_mode, the level is incremented for words that might be dropped later.
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750304
    level <= to_integer(write_addr_next - read_addr_next) mod (2 * depth);
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  end process;
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  should_drop_packet <= to_sl(enable_drop_packet) and drop_packet;
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406208
  write_addr_next_if_not_drop <= write_addr + to_int(write_ready and write_valid);
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220352
  write_addr_next <=
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26874
    write_addr_start_of_packet when should_drop_packet else write_addr_next_if_not_drop;
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915549
  read_addr_next <= read_addr + to_int(read_ready and read_valid);
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  ------------------------------------------------------------------------------
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  memory_block : block
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    constant memory_word_width : integer := width + to_int(enable_last);
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    subtype word_t is std_logic_vector(memory_word_width - 1 downto 0);
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    type mem_t is array (integer range <>) of word_t;
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69244
    signal mem : mem_t(0 to depth - 1) := (others => (others => '0'));
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    attribute ram_style of mem : signal is to_attribute(ram_type);
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2276
    signal memory_read_data, memory_write_data : word_t := (others => '0');
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  begin
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1308706
    read_data <= memory_read_data(read_data'range);
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470217
    memory_write_data(write_data'range) <= write_data;
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    assign_data : if enable_last generate
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      read_last <= memory_read_data(memory_read_data'high);
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1502782
      memory_write_data(memory_write_data'high) <= write_last;
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    end generate;
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35198
    memory : process
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    begin
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1500610
      wait until rising_edge(clk);
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12494186
      memory_read_data <= mem(to_integer(read_addr_next) mod depth);
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375152
      if write_ready and write_valid then
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1120811
        mem(to_integer(write_addr) mod depth) <= memory_write_data;
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      end if;
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    end process;
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  end block;
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  ------------------------------------------------------------------------------
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  psl_block : block
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    signal first_cycle : std_logic := '1';
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    signal fill_level : unsigned(read_addr'range);
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  begin
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1867326
    fill_level <= write_addr - read_addr;
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    ctrl : process
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    begin
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1500610
      wait until rising_edge(clk);
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750332
      first_cycle <= '0';
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    end process;
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    -- psl default clock is rising_edge(clk);
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    --
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    -- psl level_port_same_as_fill_level : assert always
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    --   level = fill_level;
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    --
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    -- Constrains start state of read_addr and write_addr to be valid.
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    -- psl level_within_range : assert always
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    --   fill_level <= depth;
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    --
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    -- To constrain start state. Otherwise read_valid can start as one, and a read
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    -- transaction occur, despite FIFO being empty.
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    -- psl not_read_valid_unless_data_in_fifo : assert always
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    --   not (read_valid = '1' and level = 0);
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    --
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    -- psl write_ready_false_if_full : assert always
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    --   level = depth -> not write_ready;
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    --
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    -- Latency since data must propagate through BRAM.
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    -- psl read_valid_goes_high_two_cycles_after_write : assert always
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    --   (write_valid and write_ready) -> next[2] (read_valid);
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    --
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    -- psl read_valid_stays_high_until_read_ready : assert always
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    --   (read_valid) -> (read_valid) until (read_ready);
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    --
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    -- psl read_data_should_be_stable_until_handshake_transaction : assert always
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    --   (not first_cycle) and prev(read_valid and not read_ready) -> stable(read_data);
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    --
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    -- psl read_last_should_be_stable_until_handshake_transaction : assert always
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    --   (not first_cycle) and prev(read_valid and not read_ready) -> stable(read_last);
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    --
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    -- psl read_valid_may_fall_only_after_handshake_transaction : assert always
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    --   first_cycle = '0' and fell(read_valid) -> prev(read_ready);
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    --
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    -- psl level_should_stay_the_same_if_there_is_both_read_and_write : assert always
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    --   {level = 2 and (read_ready and read_valid and write_ready and write_valid) = '1'}
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    --     |=> level = 2;
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    --
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    -- psl level_should_decrease_cycle_after_read_if_there_is_no_write : assert always
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    --   {level = 2 and (read_ready and read_valid and not write_valid) = '1'} |=> level = 1;
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    --
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    -- psl level_should_increase_cycle_after_write_if_there_is_no_read : assert always
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    --   {level = 2 and (write_ready and write_valid and not read_ready) = '1'} |=> level = 3;
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    -- The formal verification flow doesn't handle generics very well, so the
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    -- check below is only done if the depth is 4.
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    gen_if_depth_4 : if depth = 4 generate
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56
    begin
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      -- Check that write_ready is deasserted after 4 consecutive writes
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      -- without reads.
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      -- psl assert always
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      --       {(write_valid and not read_ready)}[*4] |=> (not write_ready);
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    end generate;
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  end block;
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end architecture;