GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/fifo/fifo_netlist_build_wrapper.vhd Lines: 0 16 0.0 %
Date: 2021-06-12 04:12:08 Branches: 0 8 0.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- A wrapper of the FIFO with only the "barebone" ports routed. To be used
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-- for size assertions in netlist builds.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity fifo_netlist_build_wrapper is
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  generic (
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    use_asynchronous_fifo : boolean;
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    width : positive;
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    depth : positive
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  );
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  port (
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    clk : in std_logic;
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    clk_read : in std_logic;
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    clk_write : in std_logic;
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    --
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    read_ready : in std_logic;
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    read_valid : out std_logic := '0';
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    read_data : out std_logic_vector(width - 1 downto 0) := (others => '0');
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    --
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    write_ready : out std_logic := '1';
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    write_valid : in std_logic;
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    write_data : in std_logic_vector(width - 1 downto 0)
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  );
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end entity;
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architecture a of fifo_netlist_build_wrapper is
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begin
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  fifo_wrapper_inst : entity work.fifo_wrapper
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    generic map (
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      use_asynchronous_fifo => use_asynchronous_fifo,
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      width => width,
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      depth => depth
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    )
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    port map (
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      clk => clk,
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      clk_read => clk_read,
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      clk_write => clk_write,
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      --
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      read_ready => read_ready,
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      read_valid => read_valid,
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      read_data => read_data,
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      --
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      write_ready => write_ready,
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      write_valid => write_valid,
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      write_data => write_data
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    );
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end architecture;