GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/fifo/fifo_wrapper.vhd Lines: 28 32 87.5 %
Date: 2021-06-12 04:12:08 Branches: 38 85 44.7 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Wrapper that selects synchronous/asynchronous FIFO or passthrough depending on on generic values.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library common;
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use common.attribute_pkg.all;
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entity fifo_wrapper is
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  generic (
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    use_asynchronous_fifo : boolean;
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    -- Generics for the FIFOs.
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    -- Note that the default values are carefully chosen. Must be exactly the same as in fifo.vhd
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    -- and asynchronous_fifo.vhd.
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    width : positive;
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    depth : natural;
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    almost_full_level : integer range 0 to depth := depth;
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    almost_empty_level : integer range 0 to depth := 0;
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    enable_last : boolean := false;
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    enable_packet_mode : boolean := false;
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    enable_drop_packet : boolean := false;
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    ram_type : ram_style_t := ram_style_auto
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  );
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  port (
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    -- This clock is used for a synchronous FIFO
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    clk : in std_logic;
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    -- These clocks are used for an asynchronous FIFO
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    clk_read : in std_logic := '0';
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    clk_write : in std_logic := '0';
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    read_ready : in  std_logic;
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    read_valid : out std_logic := '0';
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    read_data : out std_logic_vector(width - 1 downto 0) := (others => '0');
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    read_last : out std_logic := '0';
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    -- Note that this is the same as write_level for a synchronous FIFO.
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    read_level : out integer range 0 to depth := 0;
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    -- Note that for an asynchronous FIFO, this signal is in the "read" clock domain.
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    almost_empty : out std_logic := '1';
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1303
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    write_ready : out std_logic := '1';
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    write_valid : in  std_logic;
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    write_data : in  std_logic_vector(width - 1 downto 0);
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    write_last : in std_logic := '0';
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    -- Note that this is the same as read_level for a synchronous FIFO.
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    write_level : out integer range 0 to depth := 0;
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    -- Note that for an asynchronous FIFO, this signal is in the "write" clock domain.
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    almost_full : out std_logic := '0';
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    -- Note that for an asynchronous FIFO, this signal is in the "write" clock domain
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    drop_packet : in std_logic := '0'
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  );
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end entity;
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architecture a of fifo_wrapper is
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begin
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  choose_fifo : if depth = 0 generate
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    assert not enable_packet_mode report "Can not use packet mode without FIFO";
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    assert not enable_drop_packet report "Can not use drop packet without FIFO";
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    write_ready <= read_ready;
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    read_valid <= write_valid;
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    read_data <= write_data;
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    read_last <= write_last;
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  elsif use_asynchronous_fifo generate
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    ------------------------------------------------------------------------------
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    asynchronous_fifo_inst : entity work.asynchronous_fifo
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      generic map (
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        width => width,
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        depth => depth,
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        almost_full_level => almost_full_level,
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        almost_empty_level => almost_empty_level,
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        enable_last => enable_last,
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        enable_packet_mode => enable_packet_mode,
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        enable_drop_packet => enable_drop_packet,
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        ram_type => ram_type
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      )
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      port map (
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        clk_read => clk_read,
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        read_ready => read_ready,
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        read_valid => read_valid,
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        read_data => read_data,
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        read_last => read_last,
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        --
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        read_level => read_level,
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        read_almost_empty => almost_empty,
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        --
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        clk_write => clk_write,
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        write_ready => write_ready,
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        write_valid => write_valid,
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        write_data => write_data,
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        write_last => write_last,
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        --
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        write_level => write_level,
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        write_almost_full => almost_full,
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        --
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        drop_packet => drop_packet
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      );
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  else generate
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    ------------------------------------------------------------------------------
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    fifo_inst : entity work.fifo
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      generic map (
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        width => width,
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        depth => depth,
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        almost_full_level => almost_full_level,
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        almost_empty_level => almost_empty_level,
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        enable_last => enable_last,
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        enable_packet_mode => enable_packet_mode,
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        enable_drop_packet => enable_drop_packet,
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        ram_type => ram_type
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      )
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      port map (
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        clk => clk,
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        level => read_level,
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        --
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        read_ready => read_ready,
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        read_valid => read_valid,
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        read_data => read_data,
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        read_last => read_last,
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        almost_empty => almost_empty,
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        --
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        write_ready => write_ready,
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        write_valid => write_valid,
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        write_data => write_data,
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        write_last => write_last,
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        almost_full => almost_full,
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        --
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        drop_packet => drop_packet
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      );
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    write_level <= read_level;
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  end generate;
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end architecture;