GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/math/tb_unsigned_divider.vhd Lines: 39 39 100.0 %
Date: 2021-06-12 04:12:08 Branches: 159 247 64.4 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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use vunit_lib.random_pkg.all;
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context vunit_lib.vunit_context;
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context vunit_lib.data_types_context;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity tb_unsigned_divider is
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  generic (
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    dividend_width : integer;
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    divisor_width : integer;
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    runner_cfg : string
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  );
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end entity;
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architecture tb of tb_unsigned_divider is
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  signal clk : std_logic := '0';
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  signal input_ready : std_logic := '0';
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  signal input_valid : std_logic := '0';
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  signal dividend : unsigned(dividend_width - 1 downto 0);
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  signal divisor : unsigned(divisor_width - 1 downto 0);
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  signal result_ready : std_logic := '0';
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  signal result_valid : std_logic := '0';
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  signal quotient : unsigned(dividend'range);
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  signal remainder : unsigned(minimum(divisor_width, dividend_width) - 1 downto 0);
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begin
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3046526
  test_runner_watchdog(runner, 20 ms);
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3046418
  clk <= not clk after 2 ns;
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  ------------------------------------------------------------------------------
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  main : process
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    procedure run_test(dividend_tb, divisor_tb : integer) is
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    begin
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1363200
      dividend <= to_unsigned(dividend_tb, dividend'length);
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      divisor <= to_unsigned(divisor_tb, divisor'length);
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      input_valid <= '1';
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      wait until (input_ready and input_valid) = '1' and rising_edge(clk);
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      input_valid <= '0';
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      result_ready <= '1';
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      wait until (result_ready and result_valid) = '1' and rising_edge(clk);
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      result_ready <= '0';
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    end procedure;
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  begin
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    test_runner_setup(runner, runner_cfg);
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    if run("division") then
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      for dividend_tb in 0 to 2**dividend_width - 1 loop
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        for divisor_tb in 1 to 2**divisor_width - 1 loop
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          run_test(dividend_tb, divisor_tb);
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          check_equal(quotient, dividend_tb / divisor_tb, to_string(dividend_tb) & "/" & to_string(divisor_tb), line_num => 73, file_name => "tb_unsigned_divider.vhd");
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637609
          check_equal(remainder, dividend_tb rem divisor_tb, to_string(dividend_tb) & "/" & to_string(divisor_tb), line_num => 74, file_name => "tb_unsigned_divider.vhd");
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        end loop;
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      end loop;
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    elsif run("divide_by_zero") then
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      for dividend_tb in 0 to 2**dividend_width - 1 loop
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        run_test(dividend_tb, 0);
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        check_equal(quotient, 2 ** quotient'length - 1, to_string(dividend_tb) & "/0", line_num => 81, file_name => "tb_unsigned_divider.vhd"); -- Max value (all 1's)
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        -- Remainder is undefined
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      end loop;
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    end if;
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    test_runner_cleanup(runner);
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  end process;
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  ------------------------------------------------------------------------------
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  dut : entity work.unsigned_divider
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    generic map (
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      dividend_width => dividend_width,
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      divisor_width => divisor_width
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    )
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    port map (
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      clk => clk,
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      input_ready => input_ready,
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      input_valid => input_valid,
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      dividend => dividend,
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      divisor => divisor,
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      result_ready => result_ready,
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      result_valid => result_valid,
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      quotient => quotient,
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      remainder => remainder
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    );
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end architecture;