GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/reg_file/axi_lite_reg_file_wrapper.vhd Lines: 0 11 0.0 %
Date: 2021-06-12 04:12:08 Branches: 0 34 0.0 %

Line Branch Exec Source
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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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-- Wrapper, for netlist build and formal flow, that sets an appropriate generic.
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library axi;
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use axi.axi_lite_pkg.all;
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-- TODO there is some problem in our formal flow related to the work library.
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-- Doing simply "use work.reg_file_pkg.all;" does not work here. The issue seems to be
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-- isolated to the top level however, since axi_lite_reg_file.vhd uses "work" completely fine.
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--
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-- Appending "--work=reg_file" in the sby_writer.py ghdl elaborate call did not immediately solve
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-- the issue.
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library reg_file;
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use reg_file.reg_file_pkg.all;
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entity axi_lite_reg_file_wrapper is
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  port (
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    clk : in std_logic;
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    --
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    axi_lite_m2s : in axi_lite_m2s_t;
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    axi_lite_s2m : out axi_lite_s2m_t;
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    --
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    regs_up : in reg_vec_t(0 to 15 - 1);
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    regs_down : out reg_vec_t(0 to 15 - 1);
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    --
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    reg_was_read : out std_logic_vector(0 to 15 - 1);
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    reg_was_written : out std_logic_vector(0 to 15 - 1)
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  );
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end entity;
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architecture a of axi_lite_reg_file_wrapper is
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  constant regs : reg_definition_vec_t(regs_up'range) := (
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    (idx=>0, reg_type=>r),
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    (idx=>1, reg_type=>w),
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    (idx=>2, reg_type=>r_w),
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    (idx=>3, reg_type=>wpulse),
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    (idx=>4, reg_type=>r_wpulse),
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    (idx=>5, reg_type=>r),
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    (idx=>6, reg_type=>w),
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    (idx=>7, reg_type=>r_w),
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    (idx=>8, reg_type=>wpulse),
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    (idx=>9, reg_type=>r_wpulse),
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    (idx=>10, reg_type=>r),
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    (idx=>11, reg_type=>w),
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    (idx=>12, reg_type=>r_w),
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    (idx=>13, reg_type=>wpulse),
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    (idx=>14, reg_type=>r_wpulse)
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  );
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begin
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  axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
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    generic map (
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      regs => regs
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    )
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    port map (
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      clk => clk,
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      --
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      axi_lite_m2s => axi_lite_m2s,
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      axi_lite_s2m => axi_lite_s2m,
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      --
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      regs_up => regs_up,
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      regs_down => regs_down,
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      --
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      reg_was_read => reg_was_read,
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      reg_was_written => reg_was_written
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    );
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end architecture;