GCC Code Coverage Report
Directory: generated/vunit_out/preprocessed/ Exec Total Coverage
File: generated/vunit_out/preprocessed/reg_file/interrupt_register.vhd Lines: 14 14 100.0 %
Date: 2021-06-12 04:12:08 Branches: 8 11 72.7 %

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-- -------------------------------------------------------------------------------------------------
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-- Copyright (c) Lukas Vik. All rights reserved.
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--
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-- This file is part of the tsfpga project.
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-- https://tsfpga.com
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-- https://gitlab.com/tsfpga/tsfpga
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-- -------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library reg_file;
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use reg_file.reg_file_pkg.all;
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entity interrupt_register is
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  port (
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    clk : in std_logic;
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    sources : in reg_t := (others => '0');
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    mask : in reg_t := (others => '1');
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    clear : in reg_t := (others => '0');
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    status : out reg_t := (others => '0');
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    trigger : out std_logic := '0'
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  );
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end entity;
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architecture a of interrupt_register is
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begin
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  main : process
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    variable status_next : reg_t := (others => '0');
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  begin
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    wait until rising_edge(clk);
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    for idx in sources'range loop
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      if clear(idx) then
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        status_next(idx) := '0';
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      elsif sources(idx) then
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        status_next(idx) := '1';
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      else
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        status_next(idx) := status(idx);
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      end if;
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    end loop;
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    trigger <= or (status_next and mask);
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    status <= status_next;
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  end process;
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end architecture;